dsPIC30F Family Reference Manual
DS70054C-page 7-2 © 2004 Microchip Technology Inc.
7.1 Introduction
This section describes the dsPIC30F oscillator system and its operation. The dsPIC30F oscillator
system has the following modules and features:
• Various external and internal oscillator options as clock sources
• An on-chip PLL to boost internal operating frequency
• Clock switching between various clock sources
• Programmable clock postscaler for system power savings
• A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures
• Clock Control register, OSCCON
• Non-volatile configuration bits for main oscillator selection
A simplified diagram of the oscillator system is shown in Figure 7-1.
7.1.1 Oscillator System Features Summary
Oscillator Sources:
• Primary oscillator with Multiple Clock modes
• Secondary oscillator (Low Power 32 kHz Crystal oscillator)
• FRC oscillator: Fast Internal RC (8 MHz)
• LPRC oscillator: Low Power Internal RC (512 kHz)
PLL Clock Multiplier:
• Operates with Primary oscillator in XT or EC Clock modes
• Some devices permit PLL operation with internal FRC oscillator
• 4 MHz-10 MHz input frequency range
• 4x Gain mode (F
OUT = 16 MHz-40 MHz)
• 8x Gain mode (F
OUT = 32 MHz-80 MHz)
• 16x Gain mode (F
OUT = 64 MHz-120 MHz)
• PLL VCO lock indication plus ‘out of lock’ trap option
• HS/2 and HS/3 Primary oscillator modes allow greater choices of crystal frequency
(available on some devices)
Clock Scaling Options:
• Generic postscaler for device clock (divide by 4, 16, 64)
Fail-Safe Clock Monitor (FSCM):
• Detects clock failure and switches over to internal FRC oscillator
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