dsPIC30F Family Reference Manual
DS70057C-page 10-4 © 2004 Microchip Technology Inc.
10.3.6 Wake-up from Sleep on Interrupt
User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from Sleep
mode, because the interrupt source is effectively disabled. To use an interrupt as a wake-up
source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater.
Any source of interrupt that is individually enabled, using its corresponding IE control bit in the
IECx registers, can wake-up the processor from Sleep mode. When the device wakes from Sleep
mode, one of two actions may occur:
• If the assigned priority for the interrupt is less than or equal to the current CPU priority, the
device will wake-up and continue code execution from the instruction following the PWRSAV
instruction that initiated Sleep mode.
• If the assigned priority level for the interrupt source is greater than the current CPU priority,
the device will wake-up and the CPU exception process will begin. Code execution will
continue from the first instruction of the ISR.
The Sleep status bit (RCON<3>) is set upon wake-up.
10.3.7 Wake-up from Sleep on Reset
All sources of device Reset will wake the processor from Sleep mode. Any source of Reset (other
than a POR) that wakes the processor will set the Sleep status bit (RCON<3>) to indicate that
the device was previously in Sleep mode.
On a Power-on Reset, the Sleep bit is cleared.
10.3.8 Wake-up from Sleep on Watchdog Time-out
If the Watchdog Timer (WDT) is enabled and expires while the device is in Sleep mode, the
processor will wake-up. The Sleep and WDTO status bits (RCON<3>, RCON<4>) are both set
to indicate that the device resumed operation due to the WDT expiration. Note that this event
does not reset the device. Operation continues from the instruction following the PWRSAV
instruction that initiated Sleep mode.
10.4 Idle Mode
User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from Idle
mode, because the interrupt source is effectively disabled. To use an interrupt as a wake-up
source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater.
When the device enters Idle mode, the following events occur:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source will remain active and peripheral modules, by default, will
continue to operate normally from the system clock source. Peripherals can optionally be
shutdown in Idle mode using their ‘stop-in-idle’ control bit. (See peripheral descriptions for
further details.)
• If the WDT or FSCM is enabled, the LPRC will also remain active.
The processor will wake from Idle mode on the following events:
• On any interrupt that is individually enabled.
• On any source of device Reset.
• On a WDT time-out.
Upon wake-up from Idle, the clock is re-applied to the CPU and instruction execution begins
immediately starting with the instruction following the PWRSAV instruction, or the first instruction
in the ISR.
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