© 2004 Microchip Technology Inc. DS70057C-page 10-3
Section 10. WDT and Power Saving Modes
WDT and Power
Saving Modes
10
10.3.2 Delay on Wake-up from Sleep
The power-up and oscillator start-up delays associated with waking up from Sleep mode are
shown in Table 10-1. In all cases, the POR delay time (T
POR = 10 µs nominal) is applied to allow
internal device circuits to stabilize before the internal system Reset signal, SYSRST
, is released.
Table 10-1: Delay Times for Exit from Sleep Mode
10.3.3 Wake-up from Sleep Mode with Crystal Oscillator or PLL
If the system clock source is derived from a crystal oscillator and/or the PLL, then the Oscillator
Start-up Timer (OST) and/or PLL lock times must be applied before the system clock source is
made available to the device. As an exception to this rule, no oscillator delays are necessary if
the system clock source is the LP oscillator and it was running while in Sleep mode. Note that in
spite of various delays applied, the crystal oscillator (and PLL) may not be up and running at the
end of the POR delay.
10.3.4 FSCM Delay and Sleep Mode
If the following conditions are true, a nominal 100 µs delay (TFSCM) will be applied after the POR
delay expires when waking from Sleep mode:
• The oscillator was shutdown while in Sleep mode.
• The system clock is derived from a crystal oscillator source and/or the PLL.
The FSCM delay provides time for the OST to expire and the PLL to stabilize before device
execution resumes in most cases. If the FSCM is enabled, it will begin to monitor the system
clock source after the FSCM delay expires.
10.3.5 Slow Oscillator Start-up
The OST and PLL lock times may not have expired when the power-up delays have expired.
If the FSCM is enabled, then the device will detect this condition as a clock failure and a clock
fail trap will occur. The device will switch to the FRC oscillator and the user can re-enable the
crystal oscillator source in the clock failure Trap Service Routine.
If FSCM is NOT enabled, then the device will simply not start executing code until the clock is
stable. From the user’s perspective, the device will appear to be in Sleep until the oscillator clock
has started.
Clock Source
SYSRST
Delay
Oscillator
Delay
FSCM Delay Notes
EC, EXTRC T
POR ——1
EC + PLL T
POR TLOCK TFSCM 1, 3, 4
XT + PLL T
POR TOST + TLOCK TFSCM 1, 2, 3, 4
XT, HS, XTL T
POR TOST TFSCM 1, 2, 4
LP (OFF during Sleep) T
POR TOST TFSCM 1, 2, 4
LP (ON during Sleep) T
POR ——1
FRC, LPRC T
POR ——1
Note 1: T
POR = Power-on Reset delay (10 µs nominal).
2: T
OST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods
before releasing the oscillator clock to the system.
3: T
LOCK = PLL lock time (20 µs nominal).
4: T
FSCM = Fail-Safe Clock Monitor delay (100 µs nominal).
Note: Please refer to the “Electrical Specifications” section of the dsPIC30F device data
sheet for T
POR, TFSCM and TLOCK specification values.
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