dsPIC30F Family Reference Manual
DS70066C-page 19-18 © 2004 Microchip Technology Inc.
19.7 Using the UART for 9-bit Communication
A typical multi-processor communication protocol will differentiate between data bytes and
address/control bytes. A common scheme is to use a 9th data bit to identify whether a data byte
is address or data information. If the 9th bit is set, the data is processed as address or control
information. If the 9th bit is cleared, the received data word is processed as data associated with
the previous address/control byte.
The protocol operates as follows:
• The master device transmits a data word with the 9th bit set. The data word contains the
address of a slave device.
• All slave devices in the communication chain receive the address word and check the slave
address value.
• The slave device that was addressed will receive and process subsequent data bytes sent
by the master device. All other slave devices will discard subsequent data bytes until a new
address word (9th bit set) is received.
19.7.1 ADDEN Control Bit
The UART receiver has an Address Detect mode which allows it to ignore data words with the
9th bit cleared. This reduces the interrupt overhead, since data words with the 9th bit cleared are
not buffered. This feature is enabled by setting the ADDEN bit (UxSTA<5>).
The UART must be configured for 9-bit data to use the Address Detect mode. The ADDEN bit
has no effect when the receiver is configured in 8-bit Data mode.
19.7.2 Setup for 9-bit Transmit
The setup procedure for 9-bit transmission is identical to the 8-bit Transmit modes, except
that PDSEL<1:0> (UxMODE<2:1) should be set to ‘11’ (see Section 19.5.3 “Setup for UART
Transmit”).
Word writes should be performed to the UxTXREG register (starts transmission).
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