© 2004 Microchip Technology Inc. DS70059C-page 12-21
Section 12. Timers
Timers
12
12.11 Reading and Writing into 32-bit Timers
In order for 32-bit read/write operations to be synchronized between the LSWord and MSWord
of the 32-bit timer, additional control logic and holding registers are utilized (see Figure 12-6).
Each Type C time base has a register called TMRxHLD, that is used when reading or writing the
timer register pair. The TMRxHLD registers are only used when their respective timers are
configured for 32-bit operation.
Assuming TMR3:TMR2 form a 32-bit timer pair; the user should first read the LSWord of the timer
value from the TMR2 register. The read of the LSWord will automatically transfer the contents of
TMR3 into the TMR3HLD register. The user can then read TMR3HLD to get the MSWord of the
timer value. This is shown in the example below:
Example 12-8: Reading from a 32-bit Timer
To write a value to the TMR3:TMR2 register pair, the user should first write the MSWord to the
TMR3HLD register. When the LSWord of the timer value is written to TMR2, the contents of
TMR3HLD will automatically be transferred to the TMR3 register.
12.12 Timer Operation in Power Saving States
12.12.1 Timer Operation in Sleep Mode
When the device enters Sleep mode, the system clock is disabled. If the timer module is running
from the internal clock source (F
OSC/4), it will also be disabled.
A Type A timer is different from the other timer modules because it can operate asynchronously
from an external clock source. Because of this distinction, the Type A time base module can
continue to operate during Sleep mode. To operate in Sleep mode, Type A time base must be
configured as follows:
• The Timer1 module is enabled, TON = 1 (T1CON<15>) and
• The Timer1 clock source is selected as external, TCS = 1 (T1CON<1> = 1) and
• The TSYNC bit (T1CON<2>) is set to logic ‘0’ (Asynchronous Counter mode enabled).
When all of the above conditions are met, Timer1 will continue to count and detect period
matches when the device is in Sleep mode. When a match between the timer and the period
register occurs, the TxIF bit will be set and an interrupt can be generated to optionally wake the
device from Sleep. Refer to Section 10. “Watchdog Timer and Power Saving Modes” for
further details.
12.12.2 Timer Operation in Idle Mode
When the device enters Idle mode, the system clock sources remain functional and the CPU
stops executing code. The timer modules can optionally continue to operate in Idle mode.
The TSIDL bit (TxCON<13>) selects if the timer module will stop in Idle mode, or continue to
operate normally. If TSIDL = 0, the module will continue operation in Idle mode. If TSIDL = 1, the
module will stop in Idle mode.
; The following code segment reads the 32-bit timer formed by the
; Timer3-Timer2 pair into the registers W1(MS Word) and W0(LS Word).
MOV TMR2, W0 ;Transfer the LSW into W1
MOV TMR3HLD, W1 ;Transfer the MSW from the holding register to W0
Note: Asynchronous counter operation is only supported for the Timer1 module.
To Next Page
Loading...
