© 2004 Microchip Technology Inc. DS70062C-page 15-29
Section 15. Motor Control PWM
Motor Control
PWM
15
15.8 PWM Output Override
The PWM output override bits allow the user to manually drive the PWM I/O pins to specified
logic states independent of the duty cycle comparison units. The PWM override bits are useful
when controlling various types of electrically commutated motors.
All control bits associated with the PWM output override function are contained in the OVDCON
register. The upper half of the OVDCON register contains 8 bits, POVDxx, that determine which
PWM I/O pins will be overridden. The lower half of the OVDCON register contains 8 bits,
POUTxx, that determine the state of the PWM I/O pin when it is overridden via the POVDxx bit.
The POVD bits are active-low control bits. When the POVD bits are set, the corresponding
POUTxx bit will have no effect on the PWM output. When one of the POVD bits is cleared, the
output on the corresponding PWM I/O pin will be determined by the state of the POUT bit. When
a POUT bit is set, the PWM pin will be driven to its active state. When the POUT bit is cleared,
the PWM pin will be driven to its inactive state.
15.8.1 Override Control for Complementary Output Mode
The PWM module will not allow certain overrides when a pair of PWM I/O pins are operating in
the Complementary mode. (PMODx = 0) The module will not allow both pins in the output pair
to become active simultaneously. The high-side pin in each output pair will always take priority.
15.8.2 Override Synchronization
If the OSYNC bit is set (PWMCON2<1>), all output overrides performed via the OVDCON
register will be synchronized to the PWM time base. Synchronous output overrides will occur at
the following times:
• Edge aligned mode, when PTMR is zero.
• Center aligned modes, when PTMR is zero, or
• When the value of PTMR matches PTPER.
The override synchronization function, when enabled, can be used to avoid unwanted narrow
pulses on the PWM output pins.
15.8.3 Output Override Examples
Figure 15-17 shows an example of a waveform that might be generated using the PWM output
override feature. The Figure shows a six-step commutation sequence for a BLDC motor. The
motor is driven through a 3-phase inverter as shown in Figure 15-11. When the appropriate
rotor position is detected, the PWM outputs are switched to the next commutation state in the
sequence. In this example, the PWM outputs are driven to specific logic states. The OVDCON
register values used to generate the signals in Figure 15-17 are given in Table 15-5.
The PWM duty cycle registers may be used in conjunction with the OVDCON register. The duty
cycle registers controls the current delivered to the load and the OVDCON register controls the
commutation. Such an example is shown in Figure 15-18. The OVDCON register values used
to generate the signals in Figure 15-18 are given in Table 15-6.
Note: Dead time insertion is still performed when PWM channels are overridden manually.
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