dsPIC30F Family Reference Manual
DS70051C-page 4-4 © 2004 Microchip Technology Inc.
4.2 Program Counter
The PC increments by 2 with the LSb set to ‘0’ to provide compatibility with data space
addressing. Sequential instruction words are addressed in the 4M program memory space by
PC<22:1>. Each instruction word is 24-bits wide.
The LSb of the program memory address (PC<0>) is reserved as a byte select bit for program
memory accesses from data space that use Program Space Visibility or table instructions. For
instruction fetches via the PC, the byte select bit is not required. Therefore, PC<0> is always set
to ‘0’.
An instruction fetch example is shown in Figure 4-2. Note that incrementing PC<22:1> by one is
equivalent to adding 2 to PC<22:0>.
Figure 4-2: Instruction Fetch Example
4.3 Data Access from Program Memory
There are two methods by which data can be transferred between the program memory and data
memory spaces: via special table instructions, or through the remapping of a 32-Kbyte program
space page into the upper half of data space. The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the LSWord of any address within program space without going
through data space, which is preferable for some applications. The TBLRDH and TBLWTH
instructions are the only method whereby the upper 8-bits of a program word can be accessed
as data.
22
0
Program Counter
0
0x000000
0x7FFFFE
24-bits
Instruction
Instruction
23
+1
(1)
Note 1:
Increment of PC<22:1> is equivalent to PC<22:0>+2.
24
23
User
Space
Latch
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