Microchip Technology dsPIC30F - Programmable Oscillator Postscaler

© 2004 Microchip Technology Inc. DS70054C-page 7-21
Section 7. Oscillator
Oscillator
7
7.15.2 FSCM and Slow Oscillator Start-up
If the chosen device oscillator has a slow start-up time coming out of POR, BOR or Sleep mode,
it is possible that the FSCM delay will expire before the oscillator has started. In this case, the
FSCM will initiate a clock failure trap. As this happens, the COSC<1:0> bits (OSCCON<13:12>)
are loaded with the FRC oscillator selection. This will effectively shut-off the original oscillator that
was trying to start. The user can detect this situation and initiate a clock switch back to the
desired oscillator in the Trap Service Routine.
7.15.3 FSCM and WDT
In the event of a clock failure, the WDT is unaffected and continues to run on the LPRC clock.
7.16 Programmable Oscillator Postscaler
The postscaler allows the user to save power by lowering the frequency of the clock which feeds
the CPU and the peripherals. Postscale values can be changed at any time via the POST<1:0>
control bits (OSCCON<7:6>).
To ensure a clean clock transition, there is some delay before a clock change occurs. The clock
postscaler does not change the clock selection multiplexer until a falling edge on the divide-by-64
output occurs. In effect, the switching delay could be up to 64 system clock cycles depending on
when the POST<1:0> control bits are written. Figure 7-13 shows the postscaler operation for
three different postscaler changes.
Figure 7-12: Programmable Oscillator Postscaler
Counter
div. by 4
div. by 16
div. by 64
System
POST1
POST0
00
01
10
11
Clock Input
Postscaled
System Clock
(from Clock Switch
and Control Logic)
Note: The system clock input can be any available source