dsPIC30F Family Reference Manual
DS70059C-page 12-14 © 2004 Microchip Technology Inc.
12.5 Timer Prescalers
The input clock (FOSC/4 or external clock) to all 16-bit timers has prescale options of 1:1, 1:8,
1:64 and 1:256. The clock prescaler is selected using the TCKPS<1:0> control bits
(TxCON<5:4>). The prescaler counter is cleared when any of the following occurs:
• A write to the TMRx register
• Clearing TON (TxCON<15>) to ‘0’
• Any device Reset
12.6 Timer Interrupts
A 16-bit timer has the ability to generate an interrupt on a period match or falling edge of the
external gate signal, depending on the Operating mode.
The TxIF bit is set when one of the following conditions is true:
• The timer count matches the respective period register and the timer module is not
operating in Gated Time Accumulation mode.
• The falling edge of the “gate” signal is detected when the timer is operating in Gated Time
Accumulation mode.
The TxIF bit must be cleared in software.
A timer is enabled as a source of interrupt via the respective timer interrupt enable bit, TxIE.
Furthermore, the interrupt priority level bits (TxIP<2:0>) must be written with a non-zero value in
order for the timer to be a source of interrupt. Refer to Section 6. “Reset Interrupts” for further
details.
Figure 12-5: Interrupt Timing for Timer Period Match
Note: The TMRx register is not cleared when TxCON is written.
Note: A special case occurs when the period register is loaded with 0x0000 and the timer
is enabled. No timer interrupts will be generated for this configuration.
TxIF
0003 000547FE 47FF 4800 000047FD
TMR2
0004
1 Instruction Cycle (TCY)
4800
PR2
0002
TMR2 Resets Here
0001
Cleared by User
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