© 2004 Microchip Technology Inc. DS70050C-page 3-5
Section 3. Data Memory
Data Memory
3
3.2 Data Space Address Generator Units (AGUs)
The dsPIC30F contains an X AGU and a Y AGU for generating data memory addresses. Both X
and Y AGUs can generate any effective address (EA) within a 64-Kbyte range. However, EAs
that are outside the physical memory provided will return all zeros for data reads and data writes
to those locations will have no effect. Furthermore, an address error trap will be generated. For
more information on address error traps, refer to Section 6. “Reset Interrupts”.
3.2.1 X Address Generator Unit
The X AGU is used by all instructions and supports all Addressing modes. The X AGU consists
of a read AGU (X RAGU) and a write AGU (X WAGU), which operate independently on separate
read and write buses during different phases of the instruction cycle. The X read data bus is the
return data path for all instructions that view data space as combined X and Y address space. It
is also the X address space data path for the dual operand read instructions (DSP instruction
class). The X write data bus is the only write path to the combined X and Y data space for all
instructions.
The X RAGU starts its effective address calculation during the prior instruction cycle, using
information derived from the just pre-fetched instruction. The X RAGU EA is presented to the
address bus at the beginning of the instruction cycle.
The X WAGU starts its effective address calculation at the beginning of the instruction cycle. The
EA is presented to the address bus during the write phase of the instruction.
Both the X RAGU and the X WAGU support modulo addressing.
Bit-reversed addressing is supported by the X WAGU only.
3.2.2 Y Address Generator Unit
The Y data memory space has one AGU that supports data reads from the Y data memory space.
The Y memory bus is never used for data writes. The function of the Y AGU and Y memory bus
is to support concurrent data reads for DSP class instructions.
The Y AGU timing is identical to that of the X RAGU, in that its effective address calculation starts
prior to the instruction cycle, using information derived from the pre-fetched instruction. The EA
is presented to the address bus at the beginning of the instruction cycle.
The Y AGU supports Modulo Addressing and Post-modification Addressing modes for the DSP
class of instructions that use it.
Note: The Y AGU does not support data writes. All data writes occur via the X WAGU to
the combined X and Y data spaces. The Y AGU is only used during data reads for
dual source operand DSP instructions.
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