Microchip Technology dsPIC30F - Page 66

dsPIC30F Family Reference Manual
DS70050C-page 3-6 © 2004 Microchip Technology Inc.
Figure 3-3: Data Space Access Timing
3.2.3 Address Generator Units and DSP Class Instructions
The Y AGU and Y memory data path are used in concert with the X RAGU by the DSP class of
instructions to provide two concurrent data read paths. For example, the MAC instruction can
simultaneously pre-fetch two operands to be used in the next multiplication.
The DSP class of instructions dedicates two W register pointers, W8 and W9, to always operate
through the X RAGU and address X data space independently from Y data space, plus two W
register pointers, W10 and W11, to always operate through the Y AGU and address Y data space
independently from X data space. Any data write performed by a DSP class instruction will take
place in the combined X and Y data space and the write will occur across the X-bus.
Consequently, the write can be to any address irrespective of where the EA is directed.
The Y AGU only supports Post-modification Addressing modes associated with the DSP class of
instructions. For more information on Addressing modes, please refer to the dsPIC30F Program-
mer’s Reference Manual. The Y AGU also supports modulo addressing for automated circular
buffers. All other (MCU) class instructions can access the Y data address space through the X
AGU when it is regarded as part of the composite linear space.
IR
X RAGU
X WAGU
[W7]
X Data Read
ADD MOV
Y Address
MAC SUB
[W7] [W8]+=2 [--W9]
ALU OP
ALU OP
[W10] [W9++] [W13] [W6++]
Stall Check
[W10]+=2
Stall Check
X Address
Y AGU
[W7] W10 W9 W8 W13 W9-2 W6
[W8] [W9-2]
[W10]
X Data Write [W9]
[W13]
W10
[W10]Y Data (Read)
ADD.W W0, [W7], [W10]
MOV.W W10, [W9++]
MAC W4*W5, A, W4, [W8]+=2, W5, [W10]+=2, [W13]+=2
SUB.W W4, [--W9], [W6++]
During
Stall Check
TCY
Q3