© 2004 Microchip Technology Inc. DS70066C-page 19-19
Section 19. UART
UART
19
19.7.3 Setup for 9-bit Reception Using Address Detect Mode
The setup procedure for 9-bit reception is similar to the 8-bit Receive modes, except that
PDSEL<1:0> (UxMODE<2:1) should be set to ‘11’ (see Section 19.6.4 “Setup for UART
Reception”).
The Receive Interrupt mode should be configured by writing to the URXISEL<1:0>
(UxSTA<7:6>) bits.
The procedure for using the Address Detect mode is as follows:
1. Set the ADDEN (UxSTA<5>) bit to enable address detect. Ensure that the URXISEL
control bits are configured to generate an interrupt after each received word.
2. Check each 8-bit address by reading the UxRXREG register, to determine if the device is
being addressed.
3. If this device has not been addressed, then discard the received word.
4. If this device has been addressed, clear the ADDEN bit to allow subsequent data bytes to
be read into the receive buffer and interrupt the CPU. If a long data packet is expected,
then the Receive Interrupt mode could be changed to buffer more than one data byte
between interrupts.
5. When the last data byte has been received, set the ADDEN bit so that only address bytes
will be received. Also, ensure that the URXISEL control bits are configured to generate an
interrupt after each received word.
Figure 19-8: Reception with Address Detect (ADDEN = 1)
19.8 Receiving Break Characters
The receiver will count and expect a certain number of bit times based on the values
programmed in the PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>) bits.
If the break is longer than 13 bit times, the reception is considered complete after the number of
bit times specified by PDSEL and STSEL. The URXDA bit is set, FERR is set, zeros are loaded
into the receive FIFO, interrupts are generated if appropriate and the RIDLE bit is set.
When the module receives a break signal and the receiver has detected the Start bit, the data
bits and the invalid Stop bit (which sets the FERR), the receiver must wait for a valid Stop bit
before looking for the next Start bit. It cannot assume that the break condition on the line is the
next Start bit. Break is regarded as a character containing all ‘0’s with the FERR bit set. The break
character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note
that RIDLE goes high when the Stop bit has been received.
Note: If the Address Detect mode is enabled (ADDEN = 1), the URXISEL<1:0> control
bits should be configured so that an interrupt will be generated after every received
word. Each received data word must be checked in software for an address match
immediately after reception.
Start
bit
bit1bit0
bit8 bit0Stop
bit
Start
bit bit8
Stop
bit
UxRX (pin)
Read Rcv
Buffer Reg
UxRXREG
UxRXIF
(Interrupt Flag)
Word 1
UxRXREG
Bit 8 = 0, Data Byte
Bit 8 = 1, Address Byte
Transfer
to Receive FIFO
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the UxRXREG (receive buffer)
because ADDEN = 1 and bit 8 = 0.
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