Microchip Technology dsPIC30F - Phase Locked Loop (PLL)

dsPIC30F Family Reference Manual
DS70054C-page 7-18 © 2004 Microchip Technology Inc.
7.10 Phase Locked Loop (PLL)
The PLL can be enabled for x4, x8 or x16 Operation modes using the FPR<3:0> oscillator
configuration bits. The input and output frequency ranges for each Operating mode are
summarized in Table 7-3.
Table 7-3: PLL Frequency Range
7.10.1 PLL Lock Status
The PLL circuit is able to detect when the PLL enters a phase locked state. It can also detect
when the PLL loses lock. The time delay for the PLL to achieve lock is designated as T
LOCK. The
T
LOCK value is nominally 20 µs. Refer to the “Electrical Specifications” in the specific device data
sheet for further information.
The LOCK bit is a read only status bit (OSCCON<5>) that reflects the LOCK status of the PLL.
The LOCK bit is cleared at a Power-on Reset.
7.10.1.1 Loss of PLL Lock During Clock Switching
When the PLL is selected as a destination clock source in a clock switch operation (including a
Power-on Reset), the LOCK bit is cleared. The LOCK bit is set after phase lock has been
achieved. If the PLL fails to achieve lock, then the clock switching circuit will NOT switch to the
PLL output for system clock; instead, it will continue to run with the old clock source.
7.10.1.2 Loss of PLL Lock During a Power-on Reset
If the PLL fails to achieve lock at a Power-on Reset (POR) and the Fail-Safe Clock Monitor
(FSCM) is enabled, the FRC oscillator will become the device clock source and a clock failure
trap will occur.
7.10.1.3 Loss of PLL Lock During Normal Device Operation
If the PLL loses lock during normal operation for at least 4 input clock cycles, then the LOCK bit
is cleared, indicating a loss of PLL lock. Furthermore, a clock failure trap will be generated. In this
situation, the processor continues to run using the PLL clock source. The user can switch to
another clock source in the Trap Service Routine, if desired.
Note: Some PLL output frequency ranges can be achieved that exceed the maximum
operating frequency of the dsPIC30F device. Refer to the “Electrical Specifications”
in the specific device data sheet for further details.
F
IN PLL Multiplier FOUT
4 MHz-10 MHz x4 16 MHz-40 MHz
4 MHz-10 MHz x8 32 MHz-80 MHz
4 MHz-7.5 MHz x16 64 MHz-120 MHz
Note: Refer to Section 6. “Reset Interrupts” for further details about oscillator failure
traps.
Note: A loss of PLL lock during normal device operation will generate a clock failure trap,
but the system clock source will not be changed. The FSCM does not need to be
enabled to detect the loss of lock.