dsPIC30F Family Reference Manual
DS70052C-page 5-14 © 2004 Microchip Technology Inc.
5.4.3.2 Configuration Register Write Code Example
The following code sequence can be used to modify a Device Configuration register:
; Set up a pointer to the location to be written.
MOV #tblpage(CONFIG_ADDR),W0
MOV W0
,
TBLPAG
MOV #tbloffset(CONFIG_ADDR),W0
; Get the new data to write to the configuration register
MOV #ConfigValue,W1
; Perform the table write to load the write latch
TBLWTL W1,[W0]
; Configure NVMCON for a configuration register write
MOV #0x4008,W0
MOV W0,NVMCON
; Disable interrupts, if enabled
PUSH SR
MOV #0x00E0,W0
IOR SR
; Write the KEY sequence
MOV #0x55,W0
MOV W0,NVMKEY
MOV #0xAA,W0
MOV W0,NVMKEY
; Start the programming sequence
BSET NVMCON,#WR
; Insert two NOPs after programming
NOP
NOP
; Re-enable interrupts, if required
POP SR
5.5 Data EEPROM Programming
The EEPROM block is accessed using table read and write operations similar to the program
memory. The TBLWTH and TBLRDH instructions are not required for EEPROM operations since
the memory is only 16-bits wide. The program and erase procedures for the data EEPROM are
similar to those used for the Flash program memory, except they are optimized for fast data
access. The following programming operations can be performed on the data EEPROM:
• Erase one word
• Erase one row (16 words)
• Program one word
• Program one row (16 words)
The data EEPROM is readable and writable during normal operation (full V
DD operating range).
Unlike the Flash program memory, normal program execution is not stopped during an EEPROM
program or erase operation.
EEPROM erase and program operations are performed using the NVMCON and NVMKEY
registers. The programming software is responsible for waiting for the operation to complete. The
software may detect when the EEPROM erase or programming operation is complete by one of
three methods:
• Poll the WR bit (NVMCON<15>) in software. The WR bit will be cleared when the operation
is complete.
• Poll the NVMIF bit (IFS0<12>) in software. The NVMIF bit will be set when the operation is
complete.
• Enable NVM interrupts. The CPU will be interrupted when the operation is complete.
Further programming operations can be handled in the ISR.
Note: Unexpected results will be obtained should the user attempt to read the EEPROM
while a programming or erase operation is underway.
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