dsPIC30F Family Reference Manual
DS70070B-page 23-64 © 2004 Microchip Technology Inc.
23.9.7 Programming Time Segments
Some requirements for programming of the time segments are as follows:
• Propagation Segment + Phase1 Segment > = Phase2 Segment
• Phase2 Segment > Synchronous Jump Width
Typically, the sampling of the bit should take place at about 60-70% through the bit time,
depending on the system parameters.
Example 23-2 has a 16 T
Q bit time. If we choose Synchronous Segment = 1 TQ and Propagation
Segment = 2 T
Q, setting Phase Segment 1 = 7 TQ would place the sample point at 10 TQ (62%
of the bit time) after the initial transition. This would leave 6 T
Q for phase segment 2.
Since phase segment 2 is 6, according to the rules, the SJWS<1:0> bits could be set to the
maximum of 4 T
Q. However, normally a large synchronization jump width is only necessary when
the clock generation of the different nodes is inaccurate or unstable, such as using ceramic
resonators. So a synchronization jump width of 1 is typically enough.
23.10 Interrupts
The module has several sources of interrupts. Each of these interrupts can be individually
enabled or disabled. A CiINTF register contains interrupt flags. A CiINTE register controls the
enabling of the 8 main interrupts. A special set of read only bits in the CiCTRL register
(ICODE<2:0>) can be used in combination with a jump table for efficient handling of interrupts.
All interrupts have one source, with the exception of the error interrupt. Any of the error interrupt
sources can set the error interrupt flag. The source of the error interrupt can be determined by
reading the CiINTF register.
The interrupts can be broken up into two categories: receive and transmit interrupts.
The receive related interrupts are:
• Receive interrupt
• Wake-up interrupt
• Receiver Overrun interrupt
• Receiver Warning interrupt
• Receiver Error Passive interrupt
The Transmit related interrupts are:
• Transmit interrupt
• Transmitter Warning interrupt
• Transmitter Error Passive interrupt
• Bus Off interrupt
23.10.1 Interrupt Acknowledge
Interrupts are directly associated with one or more status flags in CiINTF register. Interrupts are
pending as long as one of the corresponding flags is set. The flags in the registers must be reset
within the interrupt handler in order to handshake the interrupt. A flag can not be cleared if the
respective condition still prevails, with the exception being interrupts that are caused by a certain
value being reached in one of the error counter registers.
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