Microchip Technology dsPIC30F - PWM Update Lockout; PWM Special Event Trigger

© 2004 Microchip Technology Inc. DS70062C-page 15-35
Section 15. Motor Control PWM
Motor Control
PWM
15
Figure 15-21: Example Fault Timing, Cycle-by-Cycle Mode, Priority Operation
15.11 PWM Update Lockout
In some applications, it is important that all duty cycle and period registers be written before the
new values take effect. The update disable feature allows the user to specify when new duty
cycle and period values can be used by the module. The PWM update lockout feature is enabled
by setting the UDIS control bit (PWMCON2<0>).
The UDIS bit affects all duty cycle registers, PDC1-PDC4, and the PWM time base period
buffer, PTPER. To perform an update lockout, the user should perform the following steps:
• Set the UDIS bit.
• Write all duty cycle registers and PTPER, if applicable.
• Clear the UDIS bit to re-enable updates.
15.12 PWM Special Event Trigger
The PWM module has a special event trigger that allows A/D conversions to be synchronized to
the PWM time base. The A/D sampling and conversion time may be programmed to occur at
any point within the PWM period. The special event trigger allows the user to minimize the delay
between the time when A/D conversion results are acquired and the time when the duty cycle
value is updated.
The PWM special event trigger has one SFR, SEVTCMP, and four postscaler control bits
(SEVOPS<3:0>) to control its operation. The PTMR value for which a special event trigger
should occur is loaded into the SEVTCMP register.
When the PWM time base is in an Up/Down Counting mode, an additional control bit is required
to specify the counting phase for the special event trigger. The count phase is selected using
the SEVTDIR control bit in the MSb of SEVTCMP. If the SEVTDIR bit is cleared, the special
event trigger will occur on the upward counting cycle of the PWM time base. If the SEVTDIR bit
is set, the special event trigger will occur on the downward count cycle of the PWM time base.
The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down
Counting mode.
PWM
PTMR
FLTA
Fault state B
Duty cycle = 50%
Return to
normal
operation
FLTB
Fault state B Fault state A
Return to fault state B