dsPIC30F Family Reference Manual
DS70068C-page 21-2 © 2004 Microchip Technology Inc.
21.1 Overview
The Inter-Integrated Circuit (I
2
C) module is a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs,
display drivers, A/D converters, etc.
The I
2
C module can operate in any of the following I
2
C systems:
• Where the dsPIC30F acts as a Slave Device
• Where the dsPIC30F acts as a Master Device in a Single Master System
(Slave may also be active)
• Where the dsPIC30F acts as a Master/Slave Device in a Multi-Master System
(Bus collision detection and arbitration available)
The I
2
C module contains independent I
2
C master logic and I
2
C slave logic, each generating
interrupts based on their events. In multi-master systems, the software is simply partitioned into
master controller and slave controller.
When the I
2
C master logic is active, the slave logic remains active also, detecting the state of the
bus and potentially receiving messages from itself in a single master system or from other
masters in a multi-master system. No messages are lost during multi-master bus arbitration.
In a multi-master system, bus collision conflicts with other masters in the system are detected
and the module provides a method to terminate then restart the message.
The I
2
C module contains a baud rate generator. The I
2
C baud rate generator does not consume
other timer resources in the device.
21.1.1 Module Features
• Independent Master and Slave logic
• Multi-Master support. No messages lost in arbitration.
• Detects 7-bit and 10-bit device addresses
• Detects general call addresses as defined in the I
2
C protocol
• Bus Repeater mode. Accept all messages as a slave regardless of the address.
• Automatic SCL clock stretching provides delays for the processor to respond to a slave
data request.
• Supports 100 kHz and 400 kHz bus specifications.
Figure 21-1 shows the I
2
C module block diagram.
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