© 2004 Microchip Technology Inc. DS70061C-page 14-23
Section 14. Output Compare
Output
Compare
14
14.4 Output Compare Operation in Power Saving States
14.4.1 Output Compare Operation in Sleep Mode
When the device enters Sleep mode, the system clock is disabled. During Sleep, the output
compare channel will drive the pin to the same active state as driven prior to entering Sleep. The
module will then halt at this state.
For example, if the pin was high and the CPU entered the Sleep state, the pin will stay high.
Likewise, if the pin was low and the CPU entered the Sleep state, the pin will stay low. In both
cases when the part wakes up, the output compare module will resume operation.
14.4.2 Output Compare Operation in Idle Mode
When the device enters Idle mode, the system clock sources remain functional and the CPU
stops executing code. The OCSIDL bit (OCxCON<13>) selects if the capture module will stop in
Idle mode or continue operation in Idle mode.
•If OCSIDL = 1, the module will discontinue operation in Idle mode. The module will perform
the same procedures when stopped in Idle mode (OCxSIDL = 1) as it does for Sleep mode.
•If OCSIDL = 0, the module will continue operation in Idle only if the selected time base is
set to operate in Idle mode. The output compare channel(s) will operate during the CPU
Idle mode if the OCSIDL bit is a logic ‘0’. Furthermore, the time base must be enabled with
the respective TxSIDL bit set to a logic ‘0’.
14.5 I/O Pin Control
When the output compare module is enabled, the I/O pin direction is controlled by the compare
module. The compare module returns the I/O pin control back to the appropriate pin LAT and
TRIS control bits when it is disabled.
When the PWM with Fault Protection Input mode is enabled, the OCFx Fault pin must be
configured for an input by setting the respective TRIS SFR bit. Enabling this special PWM mode
does not configure the OCFx Fault pin as an input.
Table 14-5: Pins Associated with Output Compare Modules 1- 8
Note: The external Fault pins, if enabled for use, will continue to control the associated
OCx output pins while the device is in Sleep or Idle mode.
Pin Name
Pin
Type
Buffer
Type
Description
OC1 O — Output Compare/PWM Channel 1
OC2 O — Output Compare/PWM Channel 2
OC3 O — Output Compare/PWM Channel 3
OC4 O — Output Compare/PWM Channel 4
OC5 O — Output Compare/PWM Channel 5
OC6 O — Output Compare/PWM Channel 6
OC7 O — Output Compare/PWM Channel 7
OC8 O — Output Compare/PWM Channel 8
OCFA I ST PWM Fault Protection A Input (For Channels 1-4)
OCFB I ST PWM Fault Protection B Input (For Channels 5 -8)
Legend: ST = Schmitt Trigger input with CMOS levels, I = Input, O = Output
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