dsPIC30F Family Reference Manual
DS70061C-page 14-24 © 2004 Microchip Technology Inc.
Table 14-6: Example Register Map Associated with Output Compare Module
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
TMR2 0106 Timer2 Register
0000 0000 0000 0000
TMR3 010A Timer3 Register
0000 0000 0000 0000
PR2 010C Period Register 2
1111 1111 1111 1111
PR3 010E Period Register 3
1111 1111 1111 1111
T2CON 0110 TON
—
TSIDL
— — — — — —
TGATE TCKPS1 TCKPS0 T32
—
TCS
—
0000 0000 0000 0000
T3CON 0112 TON
—
TSIDL
— — — — — —
TGATE TCKPS1 TCKPS0
— —
TCS
—
0000 0000 0000 0000
OC1RS 0180 Output Compare 1 Secondary Register
uuuu uuuu uuuu uuuu
OC1R 0182 Output Compare 1 Register
uuuu uuuu uuuu uuuu
OC1CON 0184
— —
OCSIDL
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
0000 0000 0000 0000
OC2RS 0186 Output Compare 2 Secondary Register
uuuu uuuu uuuu uuuu
OC2R 0188 Output Compare 2 Register
uuuu uuuu uuuu uuuu
OC2CON 018A
— —
OCSIDL
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
0000 0000 0000 0000
OC3RS 018C Output Compare 3 Secondary Register
uuuu uuuu uuuu uuuu
OC3R 018E Output Compare 3 Register
uuuu uuuu uuuu uuuu
OC3CON 0190
— —
OCSIDL
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
0000 0000 0000 0000
OC4RS 0192 Output Compare 4 Secondary Register
uuuu uuuu uuuu uuuu
OC4R 0194 Output Compare 4 Register
uuuu uuuu uuuu uuuu
OC4CON 0196
— —
OCSIDL
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
0000 0000 0000 0000
OC5RS 0198 Output Compare 5 Secondary Register
uuuu uuuu uuuu uuuu
OC5R 019A Output Compare 5 Register
uuuu uuuu uuuu uuuu
OC5CON 019C
— —
OCSIDL
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
0000 0000 0000 0000
OC6RS 019E Output Compare 6 Secondary Register
uuuu uuuu uuuu uuuu
OC6R 01A0 Output Compare 6 Register
uuuu uuuu uuuu uuuu
OC6CON 01A2
— —
OCSIDL
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
0000 0000 0000 0000
OC7RS 01A4 Output Compare 7 Secondary Register
uuuu uuuu uuuu uuuu
OC7R 01A6 Output Compare 7 Register
uuuu uuuu uuuu uuuu
OC7CON
01A8
— —
OCSIDL
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
0000 0000 0000 0000
OC8RS 01AA Output Compare 8 Secondary Register
uuuu uuuu uuuu uuuu
OC8R 01AC Output Compare 8 Register
uuuu uuuu uuuu uuuu
OC8CON 01AE
— —
OCSIDL
— — — — — — — —
OCFLT OCTSEL OCM<2:0>
0000 0000 0000 0000
IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0
0000 0000 0000 0000
Legend: u = uninitialized
Note: The register map will depend on the number of output compare modules on the device. Please refer to the device data sheet for details.