dsPIC30F Family Reference Manual
DS70062C-page 15-24 © 2004 Microchip Technology Inc.
Figure 15-9: Duty Cycle Update Times in Up/Down Count Mode
Figure 15-10: Duty Cycle Update Times in Up/Down Count Mode with Double Updates
15.5 Complementary PWM Output Mode
The Complementary Output mode is used to drive inverter loads similar to the one shown in
Figure 15-11. This inverter topology is typical for ACIM and BLDC applications. In the Comple-
mentary Output mode, a pair of PWM outputs cannot be active simultaneously. Each PWM
channel and output pin pair is internally configured as shown in Figure 15-12. A dead time may
be optionally inserted during device switching where both outputs are inactive for a short period
(Refer to Section 15.6 “Dead Time Control”).
Figure 15-11: Typical Load for Complementary PWM Outputs
PTMR Value
PWM output
Duty cycle value loaded from PDCx register, CPU interrupted
New value written to PDCx register
PTIF
PTMR Value
PWM output
Duty cycle value loaded from PDCx register, CPU interrupted
New values written to PDCx register
+V
1H
1L
3 Phase
Load
2H
2L
3H
3L
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