dsPIC30F Family Reference Manual
DS70053C-page 6-14 © 2004 Microchip Technology Inc.
6.4 Interrupt Control and Status Registers
The following registers are associated with the interrupt controller:
• INTCON1, INTCON2 Registers
Global interrupt control functions are derived from these two registers. INTCON1 contains
the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the
processor trap sources. The INTCON2 register controls the external interrupt request
signal behavior and the use of the alternate vector table.
• IFSx: Interrupt Flag Status Registers
All interrupt request flags are maintained in the IFSx registers, where ‘x’ denotes the
register number. Each source of interrupt has a Status bit, which is set by the respective
peripherals or external signal and is cleared via software.
• IECx: Interrupt Enable Control Registers
All Interrupt Enable Control bits are maintained in the IECx registers, where ‘x’ denotes the
register number. These control bits are used to individually enable interrupts from the
peripherals or external signals.
• IPCx: Interrupt Priority Control Registers
Each user interrupt source can be assigned to one of eight priority levels. The IPC registers
are used to set the interrupt priority level for each source of interrupt.
• SR: CPU Status Register
The SR is not specifically part of the interrupt controller hardware, but it contains the
IPL<2:0> Status bits (SR<7:5>) that indicate the current CPU priority level. The user may
change the current CPU priority level by writing to the IPL bits.
• CORCON: Core Control Register
The CORCON is not specifically part of the interrupt controller hardware, but it contains the
IPL3 Status bit which indicates the current CPU priority level. IPL3 is a Read Only bit so
that trap events cannot be masked by the user software.
Each register is described in detail on the following pages.
6.4.1 Assignment of Interrupts to Control Registers
The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence
that they are listed in Table 6-2. For example, the INT0 (External Interrupt 0) is shown as having
vector number and a natural order priority of ‘0’. Thus, the INT0IF Status bit is found in IFS0<0>.
The INT0 interrupt uses bit 0 of the IEC0 register as its Enable bit and the IPC0<2:0> bits assign
the interrupt priority level for the INT0 interrupt.
Note: The total number and type of interrupt sources will depend on the device variant.
Refer to the specific device data sheet for further details.
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