© 2004 Microchip Technology Inc. DS70053C-page 6-15
Section 6. Interrupts
Interrupts
6
Register 6-1: SR: Status Register (In CPU)
Register 6-2: CORCON: Core Control Register
Upper Byte:
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R-0
OA OB SA SB OAB SAB DA DC
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL<2:0> RA N OV Z C
bit 7 bit 0
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU interrupt priority level is 7 (15). User interrupts disabled.
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU
interrupt priority level. The value in parentheses indicates the IPL if IPL<3> = 1.
2: The IPL<2:0> status bits are read only when NSTDIS = 1 (INTCON1<15>).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Bit can be cleared
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Upper Byte:
U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0
— — — US EDT DL<1:0>
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3 PSV RND IF
bit 7 bit 0
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority
level.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Bit can be cleared
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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