dsPIC30F Family Reference Manual
DS70053C-page 6-16 © 2004 Microchip Technology Inc.
Register 6-3: INTCON1: Interrupt Control Register 1
Upper Byte:
R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
NSTDIS
— — — — OVATE OVBTE COVTE
bit 15 bit 8
Lower Byte:
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
— — — MATHERR ADDRERR STKERR OSCFAIL —
bit 7 bit 0
bit 15 NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14-11 Unimplemented: Read as ‘0’
bit 10 OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap disabled
bit 9 OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap disabled
bit 8 COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap disabled
bit 7-5 Unimplemented: Read as ‘0’
bit 4 MATHERR: Arithmetic Error Status bit
1 = Overflow trap has occurred
0 = Overflow trap has not occurred
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
To Next Page
Loading...
