Microchip Technology dsPIC30F - Using the RCON Status Bits

dsPIC30F Family Reference Manual
DS70055C-page 8-10 © 2004 Microchip Technology Inc.
8.8 Using the RCON Status Bits
The user can read the RCON register after any device Reset to determine the cause of the
Reset.
Table 8-2 provides a summary of the Reset flag bit operation.
Table 8-2: Reset Flag Bit Operation
Note: The status bits in the RCON register should be cleared after they are read so that
the next RCON register value after a device Reset will be meaningful.
Flag Bit Set by: Cleared by:
TRAPR (RCON<15>) Trap conflict event POR
IOPWR (RCON<14>) Illegal opcode or uninitialized
W register access
POR
EXTR (RCON<7>) MCLR
Reset POR
SWR (RCON<6>) RESET instruction POR
WDTO (RCON<4>) WDT time-out PWRSAV instruction, POR
SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR
IDLE (RCON<2>) PWRSAV #IDLE instruction POR
BOR (RCON<1>) POR, BOR
POR (RCON<0>) POR
Note: All RESET flag bits may be set or cleared by the user software.