dsPIC30F Family Reference Manual
DS70070B-page 23-58 © 2004 Microchip Technology Inc.
23.7.9.2 Transmission Error Interrupts
A transmission error interrupt will be indicated by the ERRIF flag. This flag shows that an error
condition occurred. The source of the error can be determined by checking the error flags in the
CAN Interrupt Status register CiINTF. The flags in this register are related to receive and transmit
errors.
The TXWAR bit (CiINTF<10>) indicates that the Transmit Error Counter has reached the CPU
warning limit of 96. When this bit transitions from a ‘0’ to a ‘1’, it will cause the error interrupt flag
to become set. The TXWAR bit cannot be manually cleared, as it should remain as an indicator
that the Transmit Error Counter has reached the CPU warning limit of 96. The TXWAR bit will
become clear automatically if the Transmit Error Counter becomes less than or equal to 95. The
ERRIF flag can be manually cleared allowing the interrupt service routine to be exited without
affecting the TXWAR bit.
The TXEP bit (CiINTF<12>) indicates that the Transmit Error Counter has exceeded the Error
Passive limit of 127 and the module has gone to Error Passive state. When this bit transitions
froma ‘0’ to a ‘1’, it will cause the error interrupt flag to become set. The TXEP bit cannot be
manually cleared, as it should remain as an indicator that the bus is in Error Passive state. The
TXEP bit will become clear automatically if the Transmit Error Counter becomes less than or
equal to 127. The ERRIF flag can be manually cleared allowing the interrupt service routine to
be exited without affecting the TXEP bit.
The TXBO bit (CiINTF<13>) indicates that the Transmit Error Counter has exceeded 255 and the
module has gone to bus off state. When this bit transitions from a ‘0’ to a ‘1’, it will cause the error
interrupt flag to become set. The TXBO bit cannot be manually cleared, as it should remain as
an indicator that the bus is off. The ERRIF flag can be manually cleared allowing the interrupt
service routine to be exited without affecting the TXBO bit.
23.8 Error Detection
The CAN protocol provides sophisticated error detection mechanisms. The following errors can
be detected. These errors are either receive or transmit errors.
Receive errors are:
• Cyclic Redundancy Check (CRC) Error (see Section 23.6.5.1 “Cyclic Redundancy
Check (CRC) Error”)
• Bit Stuffing Bit Error (see Section 23.6.5.2 “Bit Stuffing Error”)
• lnvalid Message Received Error (see Section 23.6.5.3 “Invalid Message Received
Error”)
The transmit errors are:
• Acknowledge Error (see Section 23.7.8.1 “Acknowledge Error”)
• Form Error (see Section 23.7.8.2 “Form Error”)
• Bit Error (see Section 23.7.8.3 “Bit Error”)
23.8.1 Error States
Detected errors are made public to all other nodes via error frames. The transmission of the
erroneous message is aborted and the frame is repeated as soon as possible. Furthermore, each
CAN node is in one of the three error states “error active”, “error passive” or “bus off” according
to the value of the internal error counters. The error active state is the usual state where the bus
node can transmit messages and active error frames (made of dominant bits) without any restric-
tions. In the error passive state, messages and passive error frames (made of recessive bits)
may be transmitted. The bus off state makes it temporarily impossible for the station to participate
in the bus communication. During this state, messages can neither be received nor transmitted.
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