© 2004 Microchip Technology Inc. DS70070B-page 23-45
Section 23. CAN
CAN Module
23
23.6.4 Effects of a Reset
Upon any Reset the CAN module has to be initialized. All registers are set according to the Reset
values. The content of a received message is lost. The initialization is discussed in Section
23.5.5 “Configuration Mode”.
23.6.5 Receive Errors
The CAN module will detect the following receive errors:
• Cyclic Redundancy Check (CRC) Error
• Bit Stuffing Error
• Invalid message receive error
These receive errors do not generate an interrupt. However, the receive error counter is
incremented by one in case one of these errors occur. The RXWAR bit (CiINTF<9>) indicates
that the Receive Error Counter has reached the CPU warning limit of 96 and an interrupt is
generated.
23.6.5.1 Cyclic Redundancy Check (CRC) Error
With the Cyclic Redundancy Check, the transmitter calculates special check bits for the bit
sequence from the start of a frame until the end of the data field. This CRC sequence is
transmitted in the CRC Field. The receiving node also calculates the CRC sequence using the
same formula and performs a comparison to the received sequence. If a mismatch is detected,
a CRC error has occurred and an Error Frame is generated. The message is repeated. The
receive error interrupt counter is incremented by one. An Interrupt will only be generated if the
error counter passes a threshold value.
23.6.5.2 Bit Stuffing Error
If, between the Start -Of-Frame and the CRC Delimiter, 6 consecutive bits with the same polarity
are detected, the bit-stuffing rule has been violated. A bit-stuffing error occurs and an error frame
is generated. The message is repeated. No interrupt will be generated upon this event.
23.6.5.3 Invalid Message Received Error
If any type of error occurs during reception of a message, an error will be indicated by the IVRIF
bit (CiINTF<7>). This bit can be used (optionally with an interrupt) for autobaud detection with
the device in Listen Only mode. This error is not an indicator that any action needs to be taken,
but it does indicate that an error has occurred on the CAN bus.
23.6.5.4 Rules for Modifying the Receive Error Counter
The Receive Error Counter is modified according to the following rules:
• When the receiver detects an error, the Receive Error Counter is incremented by 1, except
when the detected error was a bit error during the transmission of an active error flag.
• When the receiver detects a “dominant” bit as the first bit after sending an error flag, the
Receive Error Counter will be incremented by 8.
• If a receiver detects a bit error while sending an active error flag, the Receive Error Counter
is incremented by 8.
• Any node tolerates up to 7 consecutive “dominant” bits after sending an active error flag or
passive error flag. After detecting the 14th consecutive “dominant” bit (in case of an Active
error flag) or after detecting the 8th consecutive “dominant” bit following a passive error
flag, and after each sequence of eight additional consecutive “dominant” bits, every trans-
mitter increases its Transmission Error Counter and every receiver increases its Receive
Error Counter by 8.
• After a successful reception of a message (reception without error up to the ACK slot and
the successful sending of the ACK bit), the Receive Error Counter is decreased by one, if
the Receive Error Counter was between 1 and 127. If the Receive Error Counter was ‘0’, it
will stay ‘0’. If the Receive Error Counter was greater than 127, it will change to a value
between 119 and 127.
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