© 2004 Microchip Technology Inc. DS70063C-page 16-17
Section 16. Quadrature Encoder Interface (QEI)
Quadrature Encoder
Interface (QEI)
16
16.6.1 Up/Down Timer Operation
The QEI timer can increment or decrement. This is a unique feature over most other timers.
When the timer is configured to count up, the timer (POSCNT) will increment until the count
matches the period register (MAXCNT). The timer resets to zero and restarts incrementing.
When the timer is configured to count down, the timer (POSCNT) will decrement until the count
matches the period register (MAXCNT). The timer resets to zero and restarts decrementing.
When the timer is configured to count down some general operation guidelines must be
followed for correct operation.
1. The MAXCNT register will serve as the period match register but because the counter is
decrementing, the desired match value is 2
count. For example, to count 0x1000 clocks,
the period register must be loaded with 0xF000.
2. On a match condition, the timer resets to zero.
Either an I/O pin or a SFR control bit specify the count direction control.
Control bit UDSRC (QEICON<0>) determines what controls the timer count direction state.
When UDSRC = 1, the timer count direction is controlled from the QEB pin. If the QEB pin is ’1’,
the count direction will be incrementing. If the QEB pin is ‘0’, the count direction will be
decrementing.
When UDSRC = 0, the timer count direction is controlled from the UPDN bit (QEICON<11>).
When UPDN = 1, the timer increments. When UPDN = 0, the timer decrements.
16.6.2 Timer External Clock
The TQCS bit (QEICON<1>) selects internal or external clock. The QEI timer can use the QEA
pin as an external clock input when TQCS is set. The QEI timer does not support the external
asynchronous counter mode. If using an external clock source the clock will automatically be
synchronized to the internal instruction cycle (T
CY).
16.6.3 Timer Gate Operation
The QEA pin functions as a timer gate when the TQGATE bit (QEICON<5>) is set and TQCS is
cleared.
In the event TQCS and TQGATE are concurrently set, the timer does not increment and does
not generate an interrupt.
16.7 Quadrature Encoder Interface Interrupts
Depending on the mode of the QEI, the QEI will generate interrupts for the following events:
• When operating in reset on match mode, QEIM<2:0> = ‘111’ and ‘101’, an interrupt occurs
on position counter rollover/underflow.
• When operating in reset on index mode, QEIM<2:0> = ‘110’ and ‘100’, an interrupt occurs
on detection of index pulse and optionally when CNTERR bit is set.
• When operating as a Timer/Counter, QEIM<2:0> = ‘001’, an interrupt occurs on a period
match event or a timer gate falling edge event when TQGATE = 1.
When a QEI interrupt event occurs, the QEIIF bit (IFS2<8>) is asserted and an interrupt will be
generated if enabled. The QEIIF bit must be cleared in software.
Enabling the QEI interrupt is accomplished via the respective enable bit, QEIIE (IEC2<8>).
To Next Page
Loading...
