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Microchip Technology dsPIC30F - Brown-Out Reset (BOR)

Microchip Technology dsPIC30F
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dsPIC30F Family Reference Manual
DS70055C-page 8-8 © 2004 Microchip Technology Inc.
8.7 Brown-out Reset (BOR)
The BOR (Brown-out Reset) module is based on an internal voltage reference circuit. The main
purpose of the BOR module is to generate a device Reset when a brown-out condition occurs.
Brown-out conditions are generally caused by glitches on the AC mains (i.e., missing waveform
portions of the AC cycles due to bad power transmission lines), or voltage sags due to excessive
current draw when a large load is energized.
The BOR module allows selection of one of the following voltage trip points:
•V
BOR = 2.0V
•V
BOR = 2.7V
•V
BOR = 4.2V
•V
BOR = 4.5V
On a BOR, the device will select the system clock source based on the device configuration bit
values (FPR<3:0>, FOS<1:0>). The PWRT time-out (T
PWRT), if enabled, will be applied before
SYSRST
is released.
If a crystal oscillator source is selected, the Brown-out Reset will invoke the Oscillator Start-up
Timer (OST). The system clock is held until OST expires. If a system clock source is derived from
the PLL, then the clock will be held until the LOCK bit (OSCCON<5>) is set.
The BOR status bit (RCON<1>) will be set to indicate that a BOR has occurred.
The BOR circuit, if enabled, will continue to operate while in Sleep or Idle modes and will reset
the device should V
DD fall below the BOR threshold voltage.
Refer to the “Electrical Specifications” section of the appropriate device data sheet for the BOR
electrical specifications.
Typical brown-out scenarios are shown in Figure 8-4. As shown, a PWRT delay (if enabled) will
be initiated each time V
DD rises above the VBOR trip point.
Figure 8-4: Brown-out Situations
Note: The BOR voltage trip points indicated here are nominal values provided for design
guidance only. Refer to the “Electrical Specifications” in the specific device data
sheet for BOR voltage limit specifications.
VDD
SYSRST
VBOR
VDD
SYSRST
VBOR
VDD
SYSRST
VBOR
T
PWRT
TPWRT
TPWRT
VDD dips before PWRT expires

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