© 2004 Microchip Technology Inc. DS70064C-page 17-11
Section 17. 10-bit A/D Converter
10-bit A/D
Converter
17
17.4 A/D Terminology and Conversion Sequence
Figure 17-2 shows a basic conversion sequence and the terms that are used. A sampling of the
analog input pin voltage is performed by sample and hold S/H amplifiers. The S/H amplifiers are
also called S/H channels. The 10-bit A/D converter has four total S/H channels, designated
CH0-CH3. The S/H channels are connected to the analog input pins via the analog input
multiplexer. The analog input multiplexer is controlled by the ADCHS register. There are two sets
of multiplexer control bits in the ADCHS register that function identically. These two sets of
control bits allow two different analog input multiplexer configurations to be programmed, which
are called MUX A and MUX B. The A/D converter can optionally switch between the MUX A and
MUX B configurations between conversions. The A/D converter can also optionally scan through
a series of analog inputs.
Sample time is the time that the A/D module’s S/H amplifier is connected to the analog input pin.
The sample time may be started manually by setting the SAMP bit (ADCON1<1>) or started
automatically by the A/D converter hardware. The sample time is ended manually by clearing the
SAMP control bit in the user software or automatically by a conversion trigger source.
Conversion time is the time required for the A/D converter to convert the voltage held by the S/H
amplifier. The A/D is disconnected from the analog input pin at the end of the sample time. The
A/D converter requires one A/D clock cycle (T
AD) to convert each bit of the result plus one
additional clock cycle. A total of 12 T
AD cycles are required to perform the complete conversion.
When the conversion time is complete, the result is loaded into one of 16 A/D Result registers
(ADCBUF0...ADCBUFF), the S/H can be reconnected to the input pin, and a CPU interrupt may
be generated.
The sum of the sample time and the A/D conversion time provides the total conversion time.
There is a minimum sample time to ensure that the S/H amplifier will give the desired accuracy
for the A/D conversion (see Section 17.16 “A/D Sampling Requirements”). Furthermore, there
are multiple input clock options for the A/D converter. The user must select an input clock option
that does not violate the minimum T
AD specification.
Figure 17-2: A/D Sample/Conversion Sequence
The 10-bit A/D converter allows many options for specifying the sample/convert sequence. The
sample/convert sequence can be very simple, such as the one shown in Figure 17-3. The
example in Figure 17-3 uses only one S/H amplifier. A more elaborate sample/convert sequence
performs multiple conversions using more than one S/H amplifier. The 10-bit A/D converter can
use two S/H amplifiers to perform two conversions in a sample/convert sequence or four S/H
amplifiers with four conversions. The number of S/H amplifiers, or channels per sample, used in
the sample/convert sequence, is determined by the CHPS control bits.
Sample Time
A/D Conversion Time
A/D Total Conversion Time
S/H amplifier is connected to the analog input pin for sampling.
S/H amplifier is disconnected from input and holds signal lever.
A/D conversion is started by the conversion trigger source.
A/D conversion complete,
result is loaded into A/D result buffer.
Optionally generate interrupt.
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