dsPIC30F Family Reference Manual
DS70049C-page 2-18 © 2004 Microchip Technology Inc.
2.6 DSP Engine
The DSP engine is a block of hardware which is fed data from the W register array but contains
its own specialized result registers. The DSP engine is driven from the same instruction decoder
that directs the MCU ALU. In addition, all operand effective addresses (EAs) are generated in the
W register array. Concurrent operation with MCU instruction flow is not possible, though both the
MCU ALU and DSP engine resources may be shared by all instructions in the instruction set.
The DSP engine consists of the following components:
• high speed 17-bit x 17-bit multiplier
•barrel shifter
• 40-bit adder/subtractor
• two target accumulator registers
• rounding logic with Selectable modes
• saturation logic with Selectable modes
Data input to the DSP engine is derived from one of the following sources:
1. Directly from the W array (registers W4, W5, W6 or W7) for dual source operand DSP
instructions. Data values for the W4, W5, W6 and W7 registers are pre-fetched via the X
and Y memory data buses.
2. From the X memory data bus for all other DSP instructions.
Data output from the DSP engine is written to one of the following destinations:
1. The target accumulator, as defined by the DSP instruction being executed.
2. The X memory data bus to any location in the data memory address space.
The DSP engine has the capability to perform inherent accumulator to accumulator operations
which require no additional data.
The MCU shift and multiply instructions use the DSP engine hardware to obtain their results. The
X memory data bus is used for data reads and writes in these operations.
A block diagram of the DSP engine is shown in Figure 2-8.
Note: For detailed code examples and instruction syntax related to this section, refer to
the dsPIC30F Programmer’s Reference Manual (DS70030).
To Next Page
Loading...
