Microchip Technology dsPIC30F - Operation During Sleep and Idle Modes; Effects of a Reset

dsPIC30F Family Reference Manual
DS70065C-page 18-30 © 2004 Microchip Technology Inc.
18.21 Operation During Sleep and Idle Modes
Sleep and Idle modes are useful for minimizing conversion noise because the digital activity of
the CPU, buses and other peripherals is minimized.
18.21.1 CPU Sleep Mode Without RC A/D Clock
When the device enters Sleep mode, all clock sources to the module are shutdown and stay at
logic ‘0’.
If Sleep occurs in the middle of a conversion, the conversion is aborted unless the A/D is clocked
from its internal RC clock generator. The converter will not resume a partially completed
conversion on exiting from Sleep mode.
Register contents are not affected by the device entering or leaving Sleep mode.
18.21.2 CPU Sleep Mode With RC A/D Clock
The A/D module can operate during Sleep mode if the A/D clock source is set to the internal A/D
RC oscillator (ADRC = 1). This eliminates digital switching noise from the conversion. When the
conversion is completed, the CONV bit will be cleared and the result loaded into the A/D result
buffer, ADCBUF.
If the A/D interrupt is enabled (ADIE = 1), the device will wake-up from Sleep when the A/D
interrupt occurs. Program execution will resume at the A/D Interrupt Service Routine if the A/D
interrupt is greater than the current CPU priority. Otherwise, execution will continue from the
instruction after the PWRSAV instruction, that placed the device in Sleep mode.
If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit
will remain set.
To minimize the effects of digital noise on the A/D module operation, the user should select a
conversion trigger source that ensures the A/D conversion will take place in Sleep mode. The
automatic conversion trigger option can be used for sampling and conversion in Sleep
(SSRC<2:0> = 111). To use the automatic conversion option, the ADON bit should be set in the
instruction prior to the PWRSAV instruction.
18.21.3 A/D Operation During CPU Idle Mode
For the A/D, the ADSIDL bit (ADCON1<13>) selects if the module will stop on Idle or continue
on Idle. If ADSIDL = 0, the module will continue normal operation when the device enters Idle
mode. If the A/D interrupt is enabled (ADIE = 1), the device will wake-up from Idle mode when
the A/D interrupt occurs. Program execution will resume at the A/D Interrupt Service Routine if
the A/D interrupt is greater than the current CPU priority. Otherwise, execution will continue from
the instruction after the PWRSAV instruction that placed the device in Idle mode.
If ADSIDL = 1, the module will stop in Idle. If the device enters Idle mode in the middle of a
conversion, the conversion is aborted. The converter will not resume a partially completed
conversion on exiting from Idle mode.
18.22 Effects of a Reset
A device Reset forces all registers to their Reset state. This forces the A/D module to be turned
off, and any conversion in progress is aborted. All pins that are multiplexed with analog inputs
will be configured as analog inputs. The corresponding TRIS bits will be set.
The values in the ADCBUF registers are not initialized during a Power-on Reset.
ADCBUF0...ADCBUFF will contain unknown data.
Note: For the A/D module to operate in Sleep, the A/D clock source must be set to RC
(ADRC = 1).