Microchip Technology dsPIC30F - A;D Sampling Requirements

dsPIC30F Family Reference Manual
DS70065C-page 18-26 © 2004 Microchip Technology Inc.
18.14.3 Example: Using Dual 8-Word Buffers
Refer to Subsection 17.15.4 in Section 17. “10-bit A/D Converter” for an example that uses
dual buffers.
18.14.4 Example: Using Alternating MUX A, MUX B Input Selections
See Subsection 17.15.5 in Section 17. “10-bit A/D Converter” for an example that uses the
MUX A and MUX B input selections.
18.15 A/D Sampling Requirements
The analog input model of the 12-bit A/D converter is shown in Figure 18-11. The total sampling
time for the A/D is a function of the internal amplifier settling time and the holding capacitor
charge time.
For the A/D converter to meet its specified accuracy, the charge holding capacitor (C
HOLD) must
be allowed to fully charge to the voltage level on the analog input pin. The source impedance
(RS), the interconnect impedance (RIC), and the internal sampling switch (RSS) impedance
combine to directly affect the time required to charge the capacitor C
HOLD. The combined imped-
ance of the analog sources must therefore be small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects of pin leakage currents on the accuracy
of the A/D converter, the maximum recommended source impedance, R
S, is 2.5 kΩ. After the
analog input channel is selected (changed), this sampling function must be completed prior to
starting the conversion. The internal holding capacitor will be in a discharged state prior to each
sample operation.
At least 1 T
AD time period should be allowed between conversions for the sample time. For more
details, see the device electrical specifications.
Figure 18-11: 12-bit A/D Converter Analog Input Model
CPIN
VA
Rs
ANx
VT = 0.6V
V
T = 0.6V
I leakage
R
IC ≤ 250Ω
Sampling
Switch
R
SS
CHOLD
= DAC capacitance
V
SS
VDD
= 18 pF
± 500 nA
Legend: CPIN
VT
I leakage
R
IC
RSS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 2.5 kΩ.
RSS ≤ 3 kΩ