dsPIC30F Family Reference Manual
DS70054C-page 7-12 © 2004 Microchip Technology Inc.
7.7 Determining Best Values for Crystals, Clock Mode, C1, C2 and RS
The best method for selecting components is to apply a little knowledge and a lot of trial,
measurement and testing.
Crystals are usually selected by their parallel resonant frequency only, however, other parame-
ters may be important to your design, such as temperature or frequency tolerance. Application
Note AN588 “PICmicro Microcontroller Oscillator Design Guide” is an excellent reference to learn
more about crystal operation and their ordering information.
The dsPIC30F internal oscillator circuit is a parallel oscillator circuit, which requires that a parallel
resonant crystal be selected. The load capacitance is usually specified in the 22 pF to 33 pF
range. The crystal will oscillate closest to the desired frequency with a load capacitance in this
range. It may be necessary to alter these values, as described later, in order to achieve other
benefits.
The Clock mode is primarily chosen based on the desired frequency of the crystal oscillator. The
main difference between the XT, XTL and HS Oscillator modes is the gain of the internal inverter
of the oscillator circuit, which allows the different frequency ranges. In general, use the oscillator
option with the lowest possible gain that still meets specifications. This will result in lower
dynamic currents (I
DD). The frequency range of each Oscillator mode is the recommended
frequency cutoff, but the selection of a different Gain mode is acceptable, as long as a thorough
validation is performed (voltage, temperature and component variations, such as resistor,
capacitor and internal oscillator circuitry).
C1 and C2 (see Figure 7-3) should also be initially selected based on the load capacitance as
suggested by the crystal manufacturer and the tables supplied in the device data sheet. The
values given in the device data sheet can only be used as a starting point since the crystal
manufacturer, supply voltage, and other factors already mentioned may cause your circuit to
differ from the one used in the factory characterization process.
Ideally, the capacitance is chosen so that it will oscillate at the highest temperature and the lowest
V
DD that the circuit will be expected to perform under. High temperature and low VDD both have
a limiting effect on the loop gain, such that if the circuit functions at these extremes, the designer
can be more assured of proper operation at other temperatures and supply voltage
combinations. The output sine wave should not be clipped in the highest gain environment
(highest V
DD and lowest temperature) and the sine output amplitude should be large enough in
the lowest gain environment (lowest V
DD and highest temperature) to cover the logic input
requirements of the clock as listed in the device data sheet.
A method for improving start-up is to use a value of C2 greater than C1. This causes a greater
phase shift across the crystal at power-up, which speeds oscillator start-up.
Besides loading the crystal for proper frequency response, these capacitors can have the effect
of lowering loop gain if their value is increased. C2 can be selected to affect the overall gain of
the circuit. A higher C2 can lower the gain if the crystal is being over driven (also, see discussion
on Rs). Capacitance values that are too high can store and dump too much current through the
crystal, so C1 and C2 should not become excessively large. Unfortunately, measuring the
wattage through a crystal is difficult, but if you do not stray too far from the suggested values you
should not have to be concerned with this.
A series resistor, Rs, is added to the circuit if, after all other external components are selected to
satisfaction, the crystal is still being overdriven. This can be determined by looking at the OSC2
pin, which is the driven pin, with an oscilloscope. Connecting the probe to the OSC1 pin will load
the pin too much and negatively affect performance. Remember that a scope probe adds its own
capacitance to the circuit, so this may have to be accounted for in your design (i.e., if the circuit
worked best with a C2 of 22 pF and scope probe was 10 pF, a 33 pF capacitor may actually be
called for). The output signal should not be clipping or flattened. Overdriving the crystal can also
lead to the circuit jumping to a higher harmonic level or even crystal damage.
To Next Page
Loading...
