Microchip Technology dsPIC30F - CPU Clocking Scheme

dsPIC30F Family Reference Manual
DS70054C-page 7-4 © 2004 Microchip Technology Inc.
7.2 CPU Clocking Scheme
Referring to Figure 7-1, the system clock source can be provided by one of four sources. These
sources are the Primary oscillator, Secondary oscillator, Internal Fast RC (FRC) oscillator or the
Low Power RC (LPRC) oscillator. The Primary oscillator source has the option of using
the internal PLL. The frequency of the selected clock source can optionally be reduced by the
programmable clock divider. The output from the programmable clock divider becomes
the system clock source, F
OSC.
The system clock source is divided by four to produce the internal instruction cycle clock, F
CY. In
this document, the instruction cycle clock is also denoted by F
OSC/4. The timing diagram in
Figure 7-2 shows the relationship between the system clock source and instruction execution.
The internal instruction cycle clock, F
OSC/4, can be provided on the OSC2 I/O pin for some
Operating modes of the Primary oscillator (see Section 7.3 “Oscillator Configuration”).
Figure 7-2: Clock/Instruction Cycle Timing
FOSC
PC
F
CY
PC PC+2 PC+4
Fetch INST (PC)
Execute INST (PC-2) Fetch INST (PC+2)
Execute INST (PC) Fetch INST (PC+4)
Execute INST (PC+2)
TCY