dsPIC30F Family Reference Manual
DS70057C-page 10-6 © 2004 Microchip Technology Inc.
10.6 Watchdog Timer
The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a
software malfunction. The WDT is a free running timer, which runs on the internal LPRC oscillator
requiring no external components. Therefore, the WDT timer will continue to operate even if the
system clock source (e.g., the crystal oscillator) fails. A block diagram of the WDT is shown in
Figure 10-1.
Figure 10-1: WDT Block Diagram
10.6.1 Enabling and Disabling the WDT
The WDT is enabled or disabled by the FWDTEN device configuration bit in the FWDT Device
Configuration register. The FWDT Configuration register values are written during device
programming. When the FWDTEN configuration bit is set, the WDT is enabled. This is the default
value for an erased device. Refer to Section 24. “Device Configuration” for further details on
the FWDT Device Configuration register.
10.6.1.1 Software Controlled WDT
If the FWDTEN device configuration bit is set, then the WDT is always enabled. However, the
WDT can be optionally controlled in the user software when the FWDTEN configuration bit has
been programmed to ‘0’.
The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software WDT option allows the user to enable
the WDT for critical code segments and disable the WDT during non-critical segments for
maximum power savings.
LPRC
WDT Overflow
Wake-up
Reset
WDT
8-bit Watchdog Timer
512 kHz
4
Programmable Prescaler A
1:1, 1:8, 1:64, 1:512
Programmable Prescaler B
1:1, 1:2, 1:3, … 1:15, 1:16
F
WC = 128 kHz
Enable WDT
FWPSB3
FWPSB2
FWPSB1
FWPSB0
FWPSA1
FWPSA0
SWDTEN
FWDTEN
2
4
from Sleep
Reset
All Device Resets
Sleep or Idle State
LPRC
CLRWDT Instr.
PWRSAV Instr.
Control
Oscillator
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