© 2004 Microchip Technology Inc. DS70057C-page 10-7
Section 10. WDT and Power Saving Modes
WDT and Power
Saving Modes
10
10.6.2 WDT Operation
If enabled, the WDT will increment until it overflows or “times out”. A WDT time-out will force a
device Reset, except during Sleep or Idle modes. To prevent a WDT Time-out Reset, the user
must periodically clear the Watchdog Timer using the CLRWDT instruction. The CLRWDT
instruction also clears the WDT prescalers.
If the WDT times out during Sleep or Idle modes, the device will wake-up and continue code
execution from where the PWRSAV instruction was executed.
In either case, the WDTO bit (RCON<4>) will be set to indicate that the device Reset or wake-up
event was due to a WDT time-out. If the WDT wakes the CPU from Sleep or Idle mode, the Sleep
status bit (RCON<3>), or Idle status bit (RCON<2>) will also be set to indicate that the device
was previously in a Power Saving mode.
10.6.3 WDT Timer Period Selection
The WDT clock source is the internal LPRC oscillator, which has a nominal frequency of 512 kHz.
The LPRC clock is further divided by 4 to provide a 128 kHz clock to the WDT. The counter for
the WDT is 8-bits wide, so the nominal time-out period for the WDT (T
WDT) is 2 milliseconds.
10.6.3.1 WDT Prescalers
The WDT has two clock prescalers, Prescaler A and Prescaler B, to allow a wide variety of
time-out periods. Prescaler A can be configured for 1:1, 1:8, 1:64 or 1:512 divide ratios. Prescaler
B can be configured for any divide ratio from 1:1 through 1:16. Time-out periods that range
between 2 ms and 16 seconds (nominal) can be achieved using the prescalers.
The prescaler settings are selected using the FWPSA<1:0> (Prescaler A) and FWPSB<3:0>
(Prescaler B) configuration bits in the FWDT Device Configuration register. The FWPSA<1:0>
and FWPSB<3:0> values are written during device programming. For more information on the
WDT prescaler configuration bits, please refer to Section 24. “Device Configuration”.
The time-out period of the WDT is calculated as follows:
Equation 10-1: WDT Time-out Period
Note: The WDT time-out period is directly related to the frequency of the LPRC oscillator.
The frequency of the LPRC oscillator will vary as a function of device operating
voltage and temperature. Please refer to the specific dsPIC30F device data sheet
for LPRC clock frequency specifications.
WDT Period = 2 ms • Prescale A • Prescale B
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