© 2004 Microchip Technology Inc. DS70064C-page 17-31
Section 17. 10-bit A/D Converter
10-bit A/D
Converter
17
17.15 Conversion Sequence Examples
The following configuration examples show the A/D operation in different sampling and buffering
configurations. In each example, setting the ASAM bit starts automatic sampling. A conversion
trigger ends sampling and starts conversion.
17.15.1 Example: Sampling and Converting a Single Channel Multiple Times
Figure 17-11 and Table 17-2 illustrate a basic configuration of the A/D. In this case, one A/D
input, AN0, will be sampled by one sample and hold channel, CH0, and converted. The results
are stored in the ADCBUF buffer. This process repeats 16 times until the buffer is full and then
the module generates an interrupt. The entire process will then repeat.
The CHPS bits specify that only sample/hold CH0 is active. With ALTS clear, only the MUX A
inputs are active. The CH0SA bits and CH0NA bit are specified (AN0-V
REF-) as the input to the
sample/hold channel. All other input selection bits are not used.
Figure 17-14: Converting One Channel 16 Times/Interrupt
ADCLK
SAMP
ADCBUF0
TSAMP
TCONV
BSF ADCON1,ASAM
Instruction Execution
ADCBUF1
DONE
ADCBUFE
ADCBUFF
Input to CH0
AN0
TSAMP
TCONV
AN0
TSAMP
TCONV
AN0
TSAMP
TCONV
AN0
ADIF
ASAM
Conversion
Trigger