Microchip Technology dsPIC30F - Device Reset Times

© 2004 Microchip Technology Inc. DS70055C-page 8-11
Section 8. Reset
Reset
8
8.9 Device Reset Times
The Reset times for various types of device Reset are summarized in Table 8-3. Note that the
system Reset signal, SYSRST
, is released after the POR delay time and PWRT delay times
expire.
The time that the device actually begins to execute code will also depend on the system oscillator
delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and
PLL lock times occur in parallel with the applicable SYSRST
delay times.
The FSCM delay determines the time at which the FSCM begins to monitor the system clock
source after the SYSRST
signal is released.
Table 8-3: Reset Delay Times for Various Device Resets
Reset Type Clock Source SYSRST
Delay
System Clock
Delay
FSCM
Delay
Notes
POR EC, EXTRC,
FRC, LPRC
T
POR + TPWRT ——1, 2
EC + PLL T
POR + TPWRT TLOCK TFSCM 1, 2, 4, 5
XT, HS, XTL, LP T
POR + TPWRT TOST TFSCM 1, 2, 3, 5
XT + PLL T
POR + TPWRT TOST + TLOCK TFSCM 1, 2, 3, 4, 5
BOR EC, EXTRC,
FRC, LPRC
T
PWRT ——2
EC + PLL T
PWRT TLOCK TFSCM 1, 2, 4, 5
XT, HS, XTL, LP T
PWRT TOST TFSCM 1, 2, 3, 5
XT + PLL T
PWRT TOST + TLOCK TFSCM 1, 2, 3, 4, 5
MCLR
Any Clock — — —
WDT Any Clock — — —
Software Any clock — — —
Illegal Opcode Any Clock — — —
Uninitialized W Any Clock — — —
Trap Conflict Any Clock — — —
Note 1: T
POR = Power-on Reset delay (10 µs nominal).
2: T
PWRT = Additional “power-up” delay as determined by the FPWRT<1:0>
configuration bits. This delay is 0 ms, 4 ms, 16 ms or 64 ms nominal.
3: T
OST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods
before releasing the oscillator clock to the system.
4: T
LOCK = PLL lock time (20 µs nominal).
5: T
FSCM = Fail-Safe Clock Monitor delay (100 µs nominal).