dsPIC30F Family Reference Manual
DS70055C-page 8-12 © 2004 Microchip Technology Inc.
8.9.1 POR and Long Oscillator Start-up Times
The oscillator start-up circuitry and its associated delay timers is not linked to the device Reset
delays that occur at power-up. Some crystal circuits (especially low frequency crystals) will have
a relatively long start-up time. Therefore, one or more of the following conditions is possible after
SYSRST
is released:
• The oscillator circuit has not begun to oscillate.
• The oscillator start-up timer has NOT expired (if a crystal oscillator is used).
• The PLL has not achieved a LOCK (if PLL is used).
The device will not begin to execute code until a valid clock source has been released to the
system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset
delay time must be known.
8.9.2 Fail-Safe Clock Monitor (FSCM) and Device Resets
If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is
released. If a valid clock source is not available at this time, the device will automatically switch
to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service
Routine.
8.9.2.1 FSCM Delay for Crystal and PLL Clock Sources
When the system clock source is provided by a crystal oscillator and/or the PLL, a small delay,
T
FSCM, will automatically be inserted after the POR and PWRT delay times. The FSCM will not
begin to monitor the system clock source until this delay expires. The FSCM delay time is
nominally 100 µs and provides additional time for the oscillator and/or PLL to stabilize. In most
cases, the FSCM delay will prevent an oscillator failure trap at a device Reset when the PWRT
is disabled.
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