dsPIC30F Family Reference Manual
DS70064C-page 17-48 © 2004 Microchip Technology Inc.
17.21 Initialization
Example 17-7 shows a simple initialization code example for the A/D module.
In this particular configuration, all 16 analog input pins, AN0-AN15, are set up as analog inputs.
Operation in Idle mode is disabled output data is in unsigned fractional format, and AV
DD and
AV
SS are used for VREFH and VREFL. The start of sampling, as well as start of conversion
(conversion trigger), are performed manually in software. The CH0 S/H amplifier is used for
conversions. Scanning of inputs is disabled, and an interrupt occurs after every sample/convert
sequence (1 conversion result). The A/D conversion clock is T
CY/2.
Since sampling is started manually by setting the SAMP bit (ADCON1<1>) after each conversion
is complete, the auto-sample time bits, SAMC<4:0> (ADCON3<12:8>), are ignored. Moreover,
since the start of conversion (i.e., end of sampling) is also triggered manually, the SAMP bit
needs to be cleared each time a new sample needs to be converted.
Example 17-7: A/D Initialization Code Example
CLR ADPCFG ; Configure A/D port,
; all input pins are analog
MOV #0x2208,W0
MOV W0,ADCON1 ; Configure sample clock source
; and conversion trigger mode.
; Unsigned Fractional format,
; Manual conversion trigger,
; Manual start of sampling,
; Simultaneous sampling,
; No operation in IDLE mode.
CLR ADCON2 ; Configure A/D voltage reference
; and buffer fill modes.
; VREF from AVDD and AVSS,
; Inputs are not scanned,
; 1 S/H channel used,
; Interrupt every sample
CLR ADCON3 ; Configure A/D conversion clock
CLR ADCHS ; Configure input channels,
; CH0+ input is AN0.
; CHO- input is VREFL (AVss)
CLR ADCSSL ; No inputs are scanned.
BCLR IFS0,#ADIF ; Clear A/D conversion interrupt
; Configure A/D interrupt priority bits (ADIP<2:0>) here, if
; required. (default priority level is 4)
BSET IEC0,#ADIE ; Enable A/D conversion interrupt
BSET ADCON1,#ADON ; Turn on A/D
BSET ADCON1,#SAMP ; Start sampling the input
CALL DELAY ; Ensure the correct sampling time has
; elapsed before starting conversion.
BCLR ADCON1,#SAMP ; End A/D Sampling and start Conversion
: ; The DONE bit is set by hardware when
: ; the convert sequence is finished
: ; The ADIF bit will be set.
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