© 2004 Microchip Technology Inc. DS70052C-page 5-9
Section 5. Flash and EEPROM Programming
Flash and EEPROM
Programming
5
5.4 Run-Time Self-Programming (RTSP)
RTSP allows the user code to modify Flash program memory contents. RTSP is accomplished
using TBLRD (table read) and TBLWT (table write) instructions, and the NVM Control registers.
With RTSP, the user may erase program memory, 32 instructions (96 bytes) at a time and can
write program memory data, 4 instructions (12 bytes) at a time.
5.4.1 RTSP Operation
The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of
32 instructions or 96 bytes. The panel size may vary depending on the dsPIC30F device variant.
Refer to the device data sheet for further information. Typically, each panel consists of 128 rows,
or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to
program 32 instructions at one time.
Each panel of program memory contains write latches that hold 32 instructions of programming
data. These latches are not memory mapped. The only way for the user to access the write
latches is through the use of table write instructions. Prior to the actual programming operation,
the write data must be loaded into the panel write latches with table write instructions. The data
to be programmed into the panel is typically loaded in sequential order into the write latches:
instruction 0, instruction 1, etc. The instruction words loaded must always be from an ‘even’
group of four address boundaries (e.g., loading of instructions 3, 4, 5, 6 is not allowed). Another
way of stating this requirement is that the starting program memory address of the four instruc-
tions must have the 3 LSb’s equal to ‘0’. All 32 write latches must be written during a
programming operation to ensure that any old data held in the latches is overwritten.
The basic sequence for RTSP programming is to setup a table pointer, then do a series of TBLWT
instructions to load the write latches. Programming is performed by setting special bits in the
NVMCON register. 32 TBLWTL and 32 TBLWTH instructions are required to load the four instruc-
tions. If multiple, discontinuous regions of program memory need to be programmed, the table
pointer should be changed for each region and the next set of write latches written.
All of the table write operations to the Flash program memory take 2 instruction cycles each,
because only the table latches are written. The actual programming operation is initiated using
the NVMCON register.
5.4.2 Flash Programming Operations
A program/erase operation is necessary for programming or erasing the internal Flash program
memory in RTSP mode. The program or erase operation is automatically timed by the device
and is nominally 2 msec in duration. Setting the WR bit (NVMCON<15>) starts the operation
and the WR bit is automatically cleared when the operation is finished.
The CPU stalls (waits) until the programming operation is finished. The CPU will not execute
any instruction or respond to interrupts during this time. If any interrupts do occur during the
programming cycle, then they will remain pending until the cycle completes.
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