© 2004 Microchip Technology Inc. DS70050C-page 3-7
Section 3. Data Memory
Data Memory
3
3.2.4 Data Alignment
The ISA supports both word and byte operations for all MCU instructions that access data
through the X memory AGU. The LSb of a 16-bit data address is ignored for word operations.
Word data is aligned in the little-endian format with the LSByte at the even address (LSB = 0)
and the MSByte at the odd address (LSB = 1).
For byte operations, the LSB of the data address is used to select the byte that is accessed. The
addressed byte is placed on the lower 8 bits of the internal data bus.
All effective address calculations are automatically adjusted depending on whether a byte or a
word access is performed. For example, an address will be incremented by 2 for a word
operation that post-increments the address pointer.
Figure 3-4: Data Alignment
3.3 Modulo Addressing
Modulo, or circular addressing provides an automated means to support circular data buffers
using hardware. The objective is to remove the need for software to perform data address
boundary checks when executing tightly looped code as is typical in many DSP algorithms.
Any W register, except W15, can be selected as the pointer to the modulo buffer. The modulo
hardware performs boundary checks on the address held in the selected W register and
automatically adjusts the pointer value at the buffer boundaries, when required.
dsPIC30F modulo addressing can operate in either data or program space (since the data
pointer mechanism is essentially the same for both). One circular buffer can be supported in each
of the X (which also provides the pointers into Program space) and Y data spaces.
The modulo data buffer length can be any size up to 32K words. The modulo buffer logic supports
buffers using word or byte sized data. However, the modulo logic only performs address bound-
ary checks at word address boundaries, so the length of a byte modulo buffer must be even. In
addition, byte-sized modulo buffers cannot be implemented using the Y AGU because byte
access is not supported via the Y memory data bus.
Note: All word accesses must be aligned to an even address (LSB = 0). Misaligned word
data fetches are not supported, so care must be taken when mixing byte and word
operations or translating from existing PICmicro code. Should a misaligned word
read or write be attempted, an address error trap will occur. A misaligned read
operation will complete, but a misaligned write will not take place. The trap will then
be taken, allowing the system to examine the machine state prior to execution of the
address Fault.
15 8 7 0
0001
0003
0005
0000
0002
0004
Byte 1
Byte 3
Byte 5
LSByte
MSByte
Word 0
Word 1
0006
0008
Long Word<15:0> 000A
Long Word<31:16> 000C
Byte 0
Byte 2
Byte 4
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