dsPIC30F Family Reference Manual
DS70067C-page 20-20 © 2004 Microchip Technology Inc.
20.5 Operation in Power Save Modes
The dsPIC30FXXXX family of devices has three Power modes:
• Operational mode: The core and peripherals are running.
• Power Save modes: These are invoked by the execution of the PWRSAV instruction. There
are two Power Save modes supported in the dsPIC30F family of devices. These are
specified in the PWRSAV instruction via a parameter. The two modes are:
- Sleep mode: Device clock source and entire device is shut down. This is achieved by
the following instruction.
;include device p30fxxxx.inc file
PWRSAV #SLEEP_MODE
- Idle mode: Device clock is operational, CPU and selected peripherals are shut down.
;include device p30fxxxx.inc file
PWRSAV #IDLE_MODE
20.5.1 Sleep Mode
When the device enters Sleep mode, the system clock is disabled.
20.5.1.1 Master Mode Operation
The following are a consequence of entering Sleep mode when the SPIx module is configured
for master operation:
• The baud rate generator in the SPIx module stops and is reset.
• If the SPIx module enters Sleep mode in the middle of a transmission/reception, then the
transmission/reception is aborted. Since there is no automatic way to prevent an entry into
Sleep mode if a transmission or reception is pending, the user software must synchronize
entry into Sleep with SPI module operation to avoid aborted transmissions.
• The transmitter and receiver will stop in Sleep. The transmitter or receiver does not
continue with a partially completed transmission at wake-up.
20.5.1.2 Slave Mode Operation
Since the clock pulses at SCKx are externally provided for Slave mode, the module will continue
to function in Sleep mode. It will complete any transactions during the transition into Sleep. On
completion of a transaction, the SPIRBF flag is set. Consequently, the SPIxIF bit will be set. If
SPI interrupts are enabled (SPIxIE = 1), the device will wake from Sleep. If the SPI interrupt pri-
ority level is greater than the present CPU priority level, code execution will resume at the SPIx
interrupt vector location. Otherwise, code execution will continue with the instruction following the
PWRSAV instruction that previously invoked Sleep mode. The module is not reset on entering
Sleep mode if it is operating as a slave device.
Register contents are not affected when the SPIx module is going into or coming out of Sleep
mode.
20.5.2 Idle Mode
When the device enters Idle mode, the system clock sources remain functional. The SPISIDL bit
(SPIxSTAT<13>) selects whether the module will stop or continue functioning on Idle.
• If SPISIDL = 1, the SPI module will stop communication on entering Idle mode. It will
operate in the same manner as it does in Sleep mode.
• If SPISID = 0 (default selection), the module will continue operation in Idle mode.
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