Microchip Technology dsPIC30F - Module Operation During PWRSAV Instruction; Effects of a Reset

© 2004 Microchip Technology Inc. DS70068C-page 21-49
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.9 Module Operation During PWRSAV Instruction
21.9.1 When the Device Enters Sleep Mode
When the device executes a PWRSAV 0 instruction, the device enters Sleep mode. When the
device enters Sleep mode, the master and slave module abort any pending message activity
and reset the state of the modules. Any transmission/reception that is in progress will not
continue when the device wakes from Sleep. After the device returns to Operational mode, the
master module will be in an Idle state waiting for a message command and the slave module
will be waiting for a Start condition. During Sleep, the IWCOL, I2COV and BCL bits are cleared.
Additionally, because the master functions are aborted, the SEN, RSEN, PEN, RCEN, ACKEN
and TRSTAT bits are cleared. TBF and RBF are cleared and the buffers are available at
wake-up.
There is no automatic method to prevent Sleep entry if a transmission or reception is active or
pending. The software must synchronize Sleep entry with I
2
C operation to avoid aborted
messages.
During Sleep, the slave module will not monitor the I
2
C bus. Thus, it is not possible to generate
a wake-up event based on the I
2
C bus using the I
2
C module. Other interrupt inputs, such as the
interrupt-on-change inputs can be used to detect message traffic on a I
2
C bus and cause a
device wake-up.
21.9.2 When the Device Enters Idle Mode
When the device executes a PWRSAV 1 instruction, the device enters Idle mode. The module
will enter a power saving state in Idle mode depending on the I2CSIDL bit (I2CCON<13>).
If I2CSIDL = 1, the module will enter the Power Saving mode similarly to actions while entering
Sleep mode.
If I2CSIDL = 0, the module will not enter a Power Saving mode. The module will continue to
operate normally.
21.10 Effects of a Reset
A Reset disables the I
2
C module and terminates any active or pending message activity. See
the register definitions of I2CCON and I2CSTAT for the Reset conditions of those registers.
Note: In this discussion, ‘Idle’ refers to the CPU power saving state. The lower-case ‘idle’
refers to the time when the I
2
C module is not transferring data on the bus.