© 2004 Microchip Technology Inc. DS70054C-page 7-5
Section 7. Oscillator
Oscillator
7
7.3 Oscillator Configuration
The oscillator source (and Operating mode) that is used at a device Power-on Reset event is
selected using non-volatile configuration bits. The oscillator configuration bits are located in the
F
OSC Configuration register. (Refer to Section 24. “Device Configuration” for further details.)
The FOS<1:0> configuration bits (F
OSC<9:8>) select the oscillator source that is used at a
Power-on Reset. The Primary oscillator is the default (unprogrammed) selection. The Secondary
oscillator, or one of the internal oscillators, may be chosen by programming these bit locations.
The FPR<3:0> configuration bits (F
OSC<3:0>) select the Operating mode of the Primary
oscillator. One of 13 Operating modes may be selected as shown in Table 7-1 below.
Table 7-1: Configuration Bit Values for Clock Selection
Oscillator Mode
Oscillator
Source
FOS<1:0> FPR<3:0>
OSC2 Pin
Alternate
Function
EC w/ PLL 16x Primary
1 11111I/O (Note 4)
EC w/ PLL 8x Primary
1 11110I/O
EC w/ PLL 4x Primary
1 11101I/O
ECIO Primary
1 11100I/O
EC Primary
1 11011FOSC/4
Reserved Primary
1 11010n/a
ERC Primary
1 11001FOSC/4
ERCIO Primary
1 11000I/O
XT w/ PLL 16x Primary
1 10111(Note 3)
XT w/ PLL 8x Primary
1 10110(Note 3)
XT w/ PLL 4x Primary
1 10101(Note 3)
XT Primary
1 10100(Note 3)
HS Primary
1 1001X(Note 3)
XTL Primary
1 1000X(Note 3)
LP Secondary
0 0 ————(Notes 1, 2)
FRC Internal
0 1 ————(Notes 1, 2)
LPRC Internal
1 0 ————(Notes 1, 2)
Note 1: OSC2 pin function is determined by the Primary oscillator mode selection (FPR<3:0> configuration bits).
2: Note that OSC1 pin cannot be used as an I/O pin, even if the Secondary oscillator or an internal clock
source is selected at all times.
3: In these Oscillator modes, a crystal is connected between the OSC1 and OSC2 pins.
4: This is the default Oscillator mode for an unprogrammed (erased) device. An unprogrammed configuration
bit has a value of ‘1’.
Note: Some dsPIC devices have additional oscillator configuration bits that allow FRC + PLL, HS/2 + PLL and
HS/3 + PLL oscillator configurations. These selections provide a greater variety of clock choices for the
PLL. Please refer to the specific device data sheet for available oscillator configurations.
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