Microchip Technology dsPIC30F

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Section 16. Quadrature Encoder Interface (QEI)

Quadrature Encoder

Interface (QEI)

16.13 Revision History

Revision A

This is the initial released revision of this document.

Revision B

This revision provides expanded information for the dsPIC30F Quadrature Encoder Interface

(QEI) module.

Revision C

This revision incorporates all known errata at the time of this document update.

Main Page

Table of Contents3
Section 1. Introduction11
- Introduction12
- Manual Objective12
- Device Structure13
- Development Support14
- Style and Symbol Conventions14
- Related Documents16
- Revision History17
- Introduction20
Section 2. Cpu21
- Programmer's Model22
- Software Stack Pointer26
- CPU Register Descriptions29
- Arithmetic Logic Unit (ALU)35
- DSP Engine36
- Divide Support45
- Instruction Flow Types45
- Loop Constructs48
- Address Register Dependencies53
- Related Application Notes58
- Revision History59
- Introduction62
Section 3. Data Memory63
- Data Space Address Generator Units (Agus)65
- Modulo Addressing67
- Bit-Reversed Addressing74
- Control Register Descriptions78
- Related Application Notes83
- Revision History84
Section 4. Program Memory85
- Program Memory Address Map86
- Program Counter88
- Data Access from Program Memory88
- Program Space Visibility from Data Space92
- Program Memory Writes94
- Related Application Notes95
- Revision History96
- Introduction98
- Run-Time Self-Programming (RTSP)98
Section 5. Flash and Eeprom Programming99
- Control Registers101
- Run-Time Self-Programming (RTSP)105
- Data EEPROM Programming110
- Design Tips116
- Related Application Notes117
- Revision History118
Section 6. Reset Interrupts119
- Introduction120
- Non-Maskable Traps124
- Interrupt Processing Timing129
- Interrupt Control and Status Registers132
- Interrupt Setup Procedures160
- Design Tips162
- Related Application Notes163
- Revision History164
- Introduction166
Section 7. Oscillator167
- CPU Clocking Scheme168
- Oscillator Configuration169
- Oscillator Control Register (OSCCON)170
- 11 = Primary Oscillator171
- Primary Oscillator173
- Crystal Oscillators/Ceramic Resonators174
- Determining Best Values for Crystals, Clock Mode, C1, C2 and Rs176
- External Clock Input177
- External RC Oscillator178
- Phase Locked Loop (PLL)182
- Low Power 32 Khz Crystal Oscillator183
- Oscillator Start-Up Timer (OST)183
- Internal Fast RC Oscillator (FRC)183
- Internal Low Power RC (LPRC) Oscillator184
- Fail-Safe Clock Monitor (FSCM)184
- Programmable Oscillator Postscaler185
- Clock Switching Operation186
- Design Tips190
- Related Application Notes191
- Revision History192
Section 8. Reset193
- Introduction194
- POR: Power-On Reset194
- External Reset (EXTR)199
- Software RESET Instruction (SWR)199
- Watchdog Time-Out Reset (WDTR)199
- Brown-Out Reset (BOR)200
- Using the RCON Status Bits202
- Device Reset Times203
- Device Start-Up Time Lines205
- Special Function Register Reset States208
- Design Tips209
- Related Application Notes210
- Revision History211
- Introduction214
Section 9. Low Voltage Detect (Lvd)215
- LVD Operation217
- Design Tips218
- Related Application Notes219
- Revision History220
Section 10. Watchdog Timer and Power Saving Modes221
- Introduction222
- Power Saving Modes222
- Sleep Mode222
- Idle Mode224
- Interrupts Coincident with Power Save Instructions225
- Watchdog Timer226
- Design Tips229
- Related Application Notes230
- Revision History231
Section 11. I/O Ports233
- Introduction234
- I/O Port Control Registers235
- Peripheral Multiplexing236
- Port Descriptions237
- Change Notification (CN) Pins237
- CN Operation in Sleep and Idle Modes238
- Related Application Notes241
- Revision History242
Section 12. Timers243
- Introduction244
- Timer Variants245
- Control Registers248
- Modes of Operation251
- Timer Prescalers256
- Timer Interrupts256
- Reading and Writing 16-Bit Timer Module Registers257
- Low Power 32 Khz Crystal Oscillator Input257
- 32-Bit Timer Configuration258
- 32-Bit Timer Modes of Operation260
- Reading and Writing into 32-Bit Timers263
- Timer Operation in Power Saving States263
- Peripherals Using Timer Modules264
- Design Tips266
- Related Application Notes267
- Revision History268
Section 13. Input Capture269
- Introduction270
- Input Capture Registers271
- Timer Selection272
- Input Capture Event Modes272
- Capture Buffer Operation276
- Input Capture Interrupts277
- UART Autobaud Support277
- Input Capture Operation in Power Saving States278
- I/O Pin Control278
- Design Tips280
- Related Application Notes281
- Revision History282
Section 14. Output Compare283
- Introduction284
- Output Compare Registers285
- Modes of Operation286
- Output Compare Operation in Power Saving States305
- I/O Pin Control305
- Design Tips308
- Related Application Notes309
- Revision History310
- Introduction312
Section 15. Motor Control Pwm313
- Control Registers314
- PWM Time Base326
- PWM Duty Cycle Comparison Units330
- Complementary PWM Output Mode334
- Dead Time Control335
- Independent PWM Output Mode338
- PWM Output Override339
- PWM Output and Polarity Control342
- PWM Fault Pins342
- PWM Update Lockout345
- PWM Special Event Trigger345
- Operation in Device Power Saving Modes346
- Special Features for Device Emulation347
- Related Application Notes350
- Revision History351
Section 16. Quadrature Encoder Interface (Qei)353
- Module Introduction354
- Control and Status Registers356
- Programmable Digital Noise Filters361
- Quadrature Decoder362
- 16-Bit Up/Down Position Counter364
- Using QEI as an Alternate 16-Bit Timer/Counter368
- Quadrature Encoder Interface Interrupts369
- I/O Pin Control370
- QEI Operation During Power Saving Modes371
- Effects of a Reset371
- Design Tips373
- Related Application Notes374
- Revision History375
Section 17. 10-Bit A/D Converter377
- Introduction378
- Control Registers380
- A/D Result Buffer380
- A/D Terminology and Conversion Sequence387
- A/D Module Configuration389
- Selecting the Voltage Reference Source389
- Selecting the A/D Conversion Clock389
- Selecting Analog Inputs for Sampling390
- Enabling the Module392
- Specifying the Sample/Conversion Sequence392
- How to Start Sampling393
- How to Stop Sampling and Start Conversions394
- Controlling Sample/Conversion Operation405
- Specifying How Conversion Results Are Written into the Buffer406
- Conversion Sequence Examples407
- A/D Sampling Requirements421
- Reading the A/D Result Buffer422
- Transfer Function423
- A/D Accuracy/Error423
- Connection Considerations423
- Initialization424
- Operation During Sleep and Idle Modes425
- Effects of a Reset425
- Design Tips427
- Related Application Notes428
- Revision History429
Section 18. 12-Bit A/D Converter431
- Revision History431
- Introduction432
- Control Registers434
- A/D Result Buffer434
- A/D Terminology and Conversion Sequence440
- A/D Module Configuration441
- Selecting the Voltage Reference Source441
- Selecting the A/D Conversion Clock442
- Selecting Analog Inputs for Sampling442
- Enabling the Module444
- How to Start Sampling444
- How to Stop Sampling and Start Conversions444
- Controlling Sample/Conversion Operation449
- Specifying How Conversion Results Are Written into the Buffer449
- Conversion Sequence Examples451
- A/D Sampling Requirements456
- Reading the A/D Result Buffer457
- Transfer Function458
- A/D Accuracy/Error458
- Connection Considerations458
- Initialization459
- Operation During Sleep and Idle Modes460
- Effects of a Reset460
- Design Tips462
- Related Application Notes463
- Revision History464
Section 19. Uart465
- Introduction466
- Control Registers467
- UART Baud Rate Generator (BRG)472
- UART Configuration474
- UART Transmitter475
- UART Receiver478
- Using the UART for 9-Bit Communication482
- Receiving Break Characters483
- Initialization484
- Other Features of the UART485
- UART Operation During CPU Sleep and Idle Modes485
- Design Tips487
- Related Application Notes488
- Revision History489
Section 20. Serial Peripheral Interface (Spi™)491
- Introduction492
- Status and Control Registers494
- Modes of Operation497
- SPI Master Mode Clock Frequency509
- Operation in Power Save Modes510
- Related Application Notes513
- Revision History514
Section 21. Inter-Integrated Circuit™ (I2C™)515
- Overview516
- I 2 C Bus Characteristics518
- Control and Status Registers521
- Enabling I 2 C Operation527
- Communicating as a Master in a Single Master Environment529
- Communicating as a Master in a Multi-Master Environment543
- Communicating as a Slave546
- Connection Considerations for I561
- Module Operation During PWRSAV Instruction563
- Effects of a Reset563
- Design Tips564
- Related Application Notes565
- Revision History566
Section 22. Data Converter Interface (DCI)567
- Introduction568
- Control Register Descriptions568
- Codec Interface Basics and Terminology574
- DCI Operation576
- Using the DCI Module583
- Operation in Power Saving Modes594
- Registers Associated with DCI594
- Design Tips596
- Related Application Notes597
- Revision History598
Section 23. Can Module599
- Introduction600
- Control Registers for the CAN Module600
- CAN Module Features626
- CAN Module Implementation627
- CAN Module Operation Modes634
- Message Reception637
- Transmission647
- Error Detection656
- CAN Baud Rate658
- Interrupts662
- Time-Stamping663
- CAN Module I/O663
- Operation in CPU Power Saving Modes664
- CAN Protocol Overview666
- Related Application Notes670
- Revision History671
Section 24. Device Configuration673
- Introduction674
- Device Configuration Registers674
- Configuration Bit Descriptions679
- Device Identification Registers680
- Related Application Notes681
- Revision History682
Section 25. Development Tool Support683
- Introduction684
- Microchip Hardware and Language Tools684
- Third Party Hardware/Software Tools and Application Libraries688
- Dspic30F Hardware Development Boards693
- Related Application Notes697
- Revision History698
Section 26. Appendix699
- Appendix A: I2C™ Overview700
- Appendix B: CAN Overview710
- Appendix C: Codec Protocol Overview723

Microchip Technology dsPIC30F - Revision History

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