© 2004 Microchip Technology Inc.. DS70071C-page 24-7
Section 24. Device Configuration
Device
Configuration
24
24.3 Configuration Bit Descriptions
This section provides specific functional information on each of the device configuration bits.
24.3.1 Oscillator Configuration Bits
For more information on the configuration bits found in the FOSC device configuration register,
please refer to Section 7. "Oscillator”.
24.3.2 BOR and POR Configuration Bits
The BOR and POR configuration bits found in the FBORPOR configuration register are used to
set the Brown-out Reset voltage for the device, enable the Brown-out Reset circuit, and set the
Power-up Timer delay time. For more information on these configuration bits, please refer to
Section 8. "Reset”.
24.3.3 Motor Control PWM Module Configuration Bits
The motor control PWM module configuration bits are located in the FBORPOR configuration
register and are present only on devices that have the PWM module. The configuration bits
associated with the PWM module have two functions:
1. Select the state of the PWM pins at a device Reset (high-Z or output).
2. Select the active signal polarity for the PWM pins. The polarity for the high side and low
side PWM pins may be selected independently.
For more information on these configuration bits, please refer to Section 15. "Motor Control
PWM”.
24.3.4 General Code Segment Configuration Bits
The general code segment configuration bits in the FGS configuration register are used to code
protect or write protect the user program memory space. The general code segment includes all
user program memory with the exception of the interrupt vector table space
(0x000000-0x0000FE).
If the general code segment is code protected by programming the GCP configuration bit
(FGS<1>) to a ‘0’, the device program memory cannot be read from the device using in-circuit
serial programming (ICSP), or the device programmer. Additionally, further code cannot be
programmed into the device without first erasing the entire general code segment.
When the general segment is code protected, user code can still access the program memory
data via table read instructions, or program space visibility (PSV) accesses from data space.
If the GWRP (FGS<0>) configuration bit is programmed, all writes to the user program memory
space are disabled.
24.3.4.1 General Code Segment Configuration Bit Group
The GCP and GWRP configuration bits in the FGS configuration register must be
programmed/erased as a group. If one or both of the configuration bits is programmed to a ‘0’, a
full chip erase must be performed to change the state of either bit.
Note: If the code protection configuration fuse group (FGS<GCP:GWRP>) bits have been
programmed, an erase of the entire code-protected device is only possible at
voltages, V
DD >= 4.5 volts.
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