© 2004 Microchip Technology Inc. DS70064C-page 17-29
Section 17. 10-bit A/D Converter
10-bit A/D
Converter
17
17.13 Controlling Sample/Conversion Operation
The application software may poll the SAMP and DONE bits to keep track of the A/D operations
or the module can interrupt the CPU when conversions are complete. The application software
may also abort A/D operations if necessary.
17.13.1 Monitoring Sample/Conversion Status
The SAMP (ADCON1<1>) and DONE (ADCON1<0>) bits indicate the sampling state and the
conversion state of the A/D, respectively. Generally, when the SAMP bit clears, indicating end of
sampling, the DONE bit is automatically set, indicating end of conversion. If both SAMP and
DONE are ‘0’, the A/D is in an inactive state. In some Operational modes, the SAMP bit may also
invoke and terminate sampling.
17.13.2 Generating an A/D Interrupt
The SMPI<3:0> bits control the generation of interrupts. The interrupt will occur some number of
sample/conversion sequences after starting sampling and re-occur on each equivalent number
of samples. Note that the interrupts are specified in terms of samples and not in terms of
conversions or data samples in the buffer memory.
When the SIMSAM bit specifies sequential sampling, regardless of the number of channels
specified by the CHPS bits, the module samples once for each conversion and data sample in
the buffer. Therefore, the value specified by the SMPI bits will correspond to the number of data
samples in the buffer, up to the maximum of 16.
When the SIMSAM bit specifies simultaneous sampling, the number of data samples in the buffer
is related to the CHPS bits. Algorithmically, the channels/sample times the number of samples
will result in the number of data sample entries in the buffer. To avoid loss of data in the buffer
due to overruns, the SMPI bits must be set to the desired buffer size divided by the channels per
sample.
Disabling the A/D interrupt is not done with the SMPI bits. To disable the interrupt, clear the ADIE
analog module interrupt enable bit.
17.13.3 Aborting Sampling
Clearing the SAMP bit while in Manual Sampling mode will terminate sampling, but may also start
a conversion if SSRC = 000.
Clearing the ASAM bit while in Automatic Sampling mode will not terminate an on going
sample/convert sequence, however, sampling will not automatically resume after subsequent
conversions.
17.13.4 Aborting a Conversion
Clearing the ADON bit during a conversion will abort the current conversion. The A/D Result
register pair will NOT be updated with the partially completed A/D conversion sample. That is,
the corresponding ADCBUF buffer location will continue to contain the value of the last
completed conversion (or the last value written to the buffer).
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