© 2004 Microchip Technology Inc. DS70049C-page 2-11
Section 2. CPU
CPU
2
2.4 CPU Register Descriptions
2.4.1 SR: CPU Status Register
The dsPIC30F CPU has a 16-bit status register (SR), the LSByte of which is referred to as the
lower status register (SRL). The upper byte of SR is referred to as SRH. A detailed description
of SR is shown in Register 2-1.
SRL contains all the MCU ALU operation status flags, plus the CPU interrupt priority status bits,
IPL<2:0> and the REPEAT loop active status bit, RA (SR<4>). During exception processing, SRL
is concatenated with the MSByte of the PC to form a complete word value, which is then stacked.
SRH contains the DSP Adder/Subtractor status bits, the DO loop active bit, DA (SR<9>) and the
Digit Carry bit, DC (SR<8>).
The SR bits are readable/writable with the following exceptions:
1. The DA bit (SR<8>): DA is a read only bit.
2. The RA bit (SR<4>): RA is a read only bit.
3. The OA, OB (SR<15:14>) and OAB (SR<11>) bits: These bits are read only and can only
be modified by the DSP engine hardware.
4. The SA, SB (SR<13:12>) and SAB (SR<10>) bits: These are read and clear only and can
only be set by the DSP engine hardware. Once set, they remain set until cleared by the
user, irrespective of the results from any subsequent DSP operations.
2.4.2 CORCON: Core Control Register
The CORCON register contains bits that control the operation of the DSP multiplier and DO loop
hardware. The CORCON register also contains the IPL3 status bit, which is concatenated with
IPL<2:0> (SR<7:5>), to form the CPU Interrupt Priority Level.
Note: Clearing the SAB bit will also clear both the SA and SB bits.
Note: A description of the SR bits affected by each instruction is provided in the dsPIC30F
Programmer’s Reference Manual (DS70030).
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