Microchip Technology dsPIC30F - Capture Buffer Operation

dsPIC30F Family Reference Manual
DS70060C-page 13-8 © 2004 Microchip Technology Inc.
13.4.3 Edge Detection Mode
The capture module can capture a time base count value on every rising and falling edge of the
input signal applied to the ICx pin. The Edge Detection mode is selected by setting the ICM<2:0>
(ICxCON<2:0>) bits to ‘001’. In this mode, the capture prescaler counter is not used. See
Figure 13-4 for a simplified timing diagram.
When the input capture module is configured for Edge Detection mode, the module will:
• Set the input capture interrupt flag (ICxIF) on every edge, rising and falling.
• The Interrupt-on-Capture mode bits, ICI<1:0> (ICxCON<6:5>), are not used in this mode.
Every capture event will generate an interrupt.
• No capture overflow, ICOV (ICxCON<4>), bit is generated.
As with the simple Capture Event mode, the input capture logic detects and synchronizes the
rising and falling edge of the capture pin signal on the internal phase clocks. If the rising or falling
edge has occurred, the capture module logic will write the current timer count to the capture
buffer and signal the interrupt generation logic. The respective capture channel interrupt status
flag, ICxIF, is asserted 2 instruction cycles after the capture buffer write event.
The captured timer count value will be 1 or 2 T
CY (instruction cycles) past the time of the
occurrence of the edge at the ICx pin (see Figure 13-4).
Figure 13-4: Edge Detection Mode Timing Diagram
13.5 Capture Buffer Operation
Each capture channel has an associated four-deep FIFO buffer. The ICxBUF register is the
buffer register visible to the user, as it is memory mapped.
When the input capture module is reset, ICM<2:0> = 000 (ICxCON<2:0>), the input capture logic
will:
• Clear the overflow condition flag (i.e., clear ICxOV (ICxCON<4>) to ‘0’).
• Reset the capture buffer to the empty state (i.e., clears ICBNE (ICxCON<3>) to ‘0’).
Reading the FIFO buffer under the following conditions will lead to indeterminate results:
• In the event the input capture module is first disabled and at some later time re-enabled.
• In the event a FIFO read is performed when the buffer is empty.
• After a device Reset.
There are two status flags which provide status on the FIFO buffer:
• ICBNE (ICxCON<3>): Input Capture Buffer Not Empty
• ICOV (ICxCON<4>): Input Capture Overflow
Capture Data
n+2 n+3 n+4 n+6n-2 n-1 n n+1n-3
TMRy
n
ICx pin
n+5
TCY
n+4
ICxIF Set ICxIF Set